A dual-mode power amplifier (PA) with controllable output states is presented. Leveraging the advantages of the outphasing architecture, the proposed PA can achieve high efficiency at two different power modes (saturation and backed-off). To solve the bandwidth limitation problem caused by the 1/4 and 1/2 wavelength transmission lines in traditional outphasing amplifiers, +/-phi equivalent transmission line with a low phase dispersion effect is employed. The low phase dispersion characteristic of this +/-phi equivalent transmission line is the core mechanism for bandwidth extension, which significantly reduces phase variation across the frequency band compared to traditional lambda/4/lambda/2 lines. Moreover, to reduce the mode switching complexity and ensure efficiency, a digitally controlled phase shifter is introduced into the signal conditioning circuit of a conventional outphasing PA. This DCPS-based single-input control scheme replaces the complex dual-input phase synchronization module of traditional outphasing PAs, simplifying system integration while enabling flexible dual-mode switching. In virtue of this design strategy, the output states of the amplifier can be artificially controlled with different back-off range. For demonstration, a 4.8 GHz monolithic microwave integrated circuit (MMIC) prototype is designed using a 0.25 mu m gallium arsenide (GaAs) process. Measurement results indicate that the prototype achieves a drain efficiency higher than 47% in saturated mode across the frequency range of 3.8-5.8 GHz. Additionally, a 6 dB back-off efficiency exceeding 26.5% is obtained within the frequency range of 4.2-5.8 GHz.

Integrated circuits for communications play an enabling role when it comes to outer-space exploration thanks to their small footprint and low weight1-3. However, owing to the severe irradiation effects of space energetic particles, the implementation of radiation-tolerant electronic circuits remains a challenge4-6. Here we report the observation of the space radiation effect on a satellite-based device and find that atomically thin materials are expected to accumulate minimal radiation-induced damage in principle. Accordingly, on the basis of a 4-inch wafer-scale monolayer 2D MoS2 process, we implement an atomic-layer transistor-based radiation-tolerant radio frequency (RF, 12-18 GHz) system with both transmitters and receivers for spaceborne communication. For on-orbit experiments, the 2D communication system was successfully launched to the approximately 517 km low Earth orbit. Notably, the system maintains a bit error rate (BER) of less than 10-8 in the transmitted data after 9 months of on-orbit operation, indicating substantial radiation tolerance and long stability. The lifespan of the 2D communication system is predicted to be about 271 years even on the geosynchronous orbit with a much harsher radiation environment. This work showcases the unique prospects of 2D electronics for spaceborne applications.

Low-power microwave systems with minimal losses are required due to the growing demand for more efficient communication systems. Two-dimensional semiconductors can potentially be used to create low-power microwave circuits, but the development of integrated two-dimensional microwave systems remains limited. Here we report integrated two-dimensional transmitters fabricated on four-inch monolayer molybdenum disulfide (MoS2) wafers. The transmission loss of monolayer MoS2 channel in switch is 0.51 dB, and the power consumption of the complete 16-element transmitter is 3.2 μW. The 4 × 4 phased array transmitter, which offers both communication and radar functions, exhibits a bandwidth of 6 GHz, a beam scanning angle from −35° to 35°, a transmission distance of 136 m and a standby time of 26 days when powered by a 1,000 mAh-capacity battery. Our complete board-level system has a size of around 3 × 2 cm2, and we show that it can be integrated into a small insect model. Sixteen-element integrated microwave transmitters that are fabricated on four-inch monolayer molybdenum disulfide wafers offer a low power consumption of 3.2 μW.

This paper proposes a three-stage wideband distributed low-noise amplifier (LNA) with cascode unit cells. A three-turn transformer (3-TT) is introduced to optimize the noise contribution of the common-source transistor. A multiple magnetic coupling feedback network (MMCFN) with inductive peaking technique is employed to improve the gain and noise figure (NF) at high frequency. An RC-parallel terminal circuit (TC) is proposed to replace the input matching resistor, which suppress the noise contribution of the TC. Implemented in a 28nm CMOS process, the proposed distributed amplifier achieves a peak small-signal gain of 15.3dB with a wide -3dB bandwidth across 3 to 119GHz. A GBW of 675GHz is obtained. The NF is from 4.8 to 9dB within the -3dB bandwidth. The circuit consumes a current of 65mA from a supply of 1.9V and 1.6V with a core chip area of 0.37mm(2).

A medium- or large-scale receiving antenna array using digital beamforming can achieve high-resolution direction-of-arrival (DOA) estimation at the receiver. However, it typically suffers from high cost and complexity. This paper proposes an efficient reconfigurable digital beamformer that can achieve real-time angle estimation with high accuracy while making effective use of hardware resources. The digital beamformer operates in two modes: beamforming mode and angle estimation mode. In the angle estimation mode, the phase shift steps required for beam scanning can be flexibly adjusted according to the desired angular resolution. By dynamically switching operational modes and fine-tuning the granularity of processing tasks, this architecture maximizes the efficient use of Field-Programmable Gate Array (FPGA) resources, ensuring optimal performance and flexibility in real-time signal processing applications. Simulation results show that with an input signal-to-noise ratio of 10 dB, the beamformer can complete DOA estimation with an error of less than 1° within microsecond-level delay.

Neuromorphic hardware that accurately simulates diverse neuronal behaviours could be of use in the development of edge intelligence. Hardware that incorporates synaptic plasticity—adaptive changes that strengthen or weaken synaptic connections—has been explored, but mimicking the full spectrum of learning and memory processes requires the interplay of multiple plasticity mechanisms including intrinsic plasticity. Here we show that an integrate-and-fire neuron can be created by combining a dynamic random-access memory and an inverter that are based on wafer-scale monolayer molybdenum disulfide films. In the system, the voltage in the dynamic random-access memory capacitor—that is, the neuronal membrane potential—can be modulated to emulate intrinsic plasticity. The module can also emulate the photopic and scotopic adaptation of the human visual system by dynamically adjusting its light sensitivity. We fabricate a 3 × 3 photoreceptor neuron array and demonstrate light coding and visual adaptation. We also use the neuron module to simulate a bioinspired neural network model for image recognition. An integrate-and-fire artificial neuron combining a dynamic random-access memory and an inverter based on wafer-scale monolayer molybdenum disulfide films can emulate intrinsic plasticity, the photopic and scotopic adaptation of the human visual system, and achieve temporal information encoding.

In this paper, we propose a compact quasihighlighting its innovative design approach and the associated fabrication techniques aimed at enhancing integration and performance. The discrete transistor is manufactured by a 0.35-mu m GaN high electron mobility employs a GaAs passive device process for compact and wideband flexible design. The output matching network employs a ceramic technology for high power and low to the input and output network with gold bonding wires. The PA exhibited a gain of 11 dB, a saturation power of 48 dBm, and a peak power-added efficiency of 32.8%.

The increasing need for real-time computation with low-power consumption is driving the advancement of specialized neuromorphic processors on various applications. Multi object tracking, as one of the most challenging tasks in computer vision, has gained wide attention with many solutions proposed. Nevertheless, they consume huge resources and fail to adapt to edge application scenarios with strict power and resource constraints. In this work, we propose NeuroSORT, a neuromorphic accelerator for spike-based online and real-time object tracking, which leverages spiking neural network (SNN) to solve linear assignment problem and explores the hardware acceleration on tracking algorithms. Experimental results show that the proposed accelerator reaches an accuracy of 99.43% on linear assignment task and 69.641 HOTA score on MOT17 dataset, while consuming 0.257mW energy and 0.17mm 2 area. The overall power consumption is reduced by 41.1% compared with SOTA works with equivalent performance.

As an important biomarker, ammonia exhibits a strong correlation with protein metabolism and specific organ dysfunction. Limited by the immobile instrumental structure, invasive and complicated procedures, and unsatisfactory online sensitivity and selectivity, current medical diagnosis fails to monitor this chemical in real time efficiently. Herein, we present the successful synthesis of a long-range epitaxial metal-organic framework on a millimeter domain-sized single-crystalline graphene substrate (LR-epi-MOF). With a perfect 30° epitaxial angle and a mere 2.8% coincidence site lattice mismatch between the MOF and graphene, this long-range-ordered epitaxial structure boosts the charge transfer from ammonia to the MOF and then to graphene, thereby promoting the overall charge delocalization and exhibiting extraordinary electrical global coupling properties. This unique characteristic imparts a remarkable sensitivity of 0.1 ppb toward ammonia. The sub-ppb detecting capability and high anti-interference ability enable continuous information recording of breath ammonia that is strongly correlated with the intriguing human lifestyle. Wearable electronics based on the LR-epi-MOF could accurately portray the active protein metabolism pattern in real time and provide personal assistance in health management.

This article presents a concurrent dual-band power amplifier (PA) in 130-nm SiGe BiCMOS process. A three-stage stacked BJT amplifier configuration is employed to enhance both the power gain and the output power. To achieve dual-band low-loss matching, the subquarter-wavelength-based baluns are adopted to construct the input and output matching networks. In addition, multiorder LC networks are introduced to achieve excellent dual-band interstage impedance matching. The proposed three-stage dual-band PA exhibits maximum small signal gains of 25.4 dB at 135 GHz and 21.6 dB at 210 GHz, with 3-dB bandwidths of 28 and 25 GHz, respectively. The measured results show a saturated power (Psat) of more than 13.1 dBm and 9.6 dBm and a power-added efficiency (PAE) of more than 6.75% and 3.1% over ranges of 126-154 GHz and 200-225 GHz, respectively. To the best of the authors' knowledge, the proposed PA achieves the higher Psat and PAE value than other dual-band PA operating at frequencies greater than 100 GHz with silicon-based process.

This article reports an ultrawide CMOS distributed low-noise amplifier (LNA) for ultrahigh-speed communications. The proposed LNA consists of a front single-end-to-differential distributed active balun and a subsequent differential distributed amplifier (DA). Various forms of parasitic capacitance that can degrade the high-frequency performance are carefully counteracted in this scheme. The distributed active balun is based on a cascode-cascade topology with full-band mismatch compensation techniques. The differential DA is built using a neutralized cascode amplifier, merged with inductive peaking and capacitive bootstrapping. Thanks to the use of these techniques, our scheme simultaneously achieves good results in terms of gain, noise figure (NF), and balance over an ultrawide bandwidth. The LNA prototype is designed in a 65-nm CMOS technology with an area of 1.9 x 0.7 mm( 2) . The LNA scores a 13.7-16.9-dB gain from 3 to 78 GHz while integrating all supply networks. The measured group delay is 45-91 ps over 3-78 GHz, and the NF is 5.5-7.8 dB up to 50 GHz. The differential outputs show a good balance of <0.37-dB gain error and < 3.8 degrees phase error over the full bandwidth. The chip core consumes a 72-mA current from a 1.2-V supply, and the total power consumption of the chip is 170.4 mW including the consumption on the 50- Omega load resistors.

Impact ionization effect has been demonstrated in transistors to enable sub-60 mV dec-1 subthreshold swing. However, traditionally, impact ionization in silicon devices requires a high operation voltage due to limited electrical field near the device drain, contradicting the low energy operation purpose. Here, we report a vertical subthreshold swing device composed of a graphene/silicon heterojunction drain and a silicon channel. This structure creates a low voltage avalanche impact ionization phenomenon and leads to steep switching of the silicon-based device. Experimental measurements reveal a small average subthreshold swing of 16 µV dec-1 over 6 decades of drain current and nearly hysteresis-free, and the operating voltage at which a vertical subthreshold swing occurs can be as low as 0.4 V at room temperature. Furthermore, a complementary silicon-based logic inverter is experimentally demonstrated to reach a voltage gain of 311 at a supply voltage of 2 V.

This paper proposes a multi-sampling mode capacitor DAC (CDAC) for a 12-bit 200MS/s pipelined-SAR ADC, addressing the issue of overfitting in neural network-based calibrations. By implementing normal, offset, and proportional sampling modes, the design ensures the linearity of the ADC's transfer function. The proposed CDAC utilizes a bottom-plate sampling method and a high-linearity bootstrap circuit. Simulation results demonstrate that the proposed ADC achieves an SFDR of around 75dB and an ENOB of approximately 10.8bits across all sampling modes, validating the effectiveness of the design in enhancing ADC performance.

This paper presents a high output power and low phase noise LC VCO implemented in WIN 0.15-μm GaAs process. The oscillator adopts a C-class architecture and incorporates a two-stage common source buffer. The power supply voltage of the circuit is 5V, the bias voltage is -1V, and the power consumption of the circuit is 505mW. The simulation result shows that the output frequency range of the VCO is 14.52GHz to 15.81GHz, which achieves a tuning range of 8.5%. In addition, with the help of a high Q value inductor, the VCO can achieve -90dBc/Hz at 100kHz frequency offset at 15GHz output frequency. Within the entire frequency range, the output power is higher than 20dBm. The overall layout area of the chip is 2190μm *1500μm.

Light Detection and Ranging (LiDAR) is becoming a critical requirement for future computer vision applications, such as AR/VR (iPhone-LiDAR) and ADAS (Automotive-LiDAR). A depth point-cloud input has different characteristics than a conventional RGB image input, such that the CNN depth-inference implementation is unique when compared with a standard super-resolution CNN(SR-CNN). In this brief, we present a heterogeneous AI-accelerator SoC, which is specific to depth image completion computation. Three key innovations are introduced to improve SoC’s performance. First, to accommodate the unique input data structure of a depth input, a fully-filled dataflow management engine is proposed to pre-process the RGB+Depth input, significantly improving processing element utilization (PEU). Second, to improve the efficiency of the instruction configurations of the CNN accelerator, a hardware-tiling co-processor is proposed that performs the tiling strategy of the CNN accelerator, assigning each sub-job to the PE array directly, therefore reducing the time for task assignments. Third, due to the large number of vector operations required for the post-process in the neural network, a RISC-V core is incorporated to execute vector computations better. The SoC is implemented in 40nm CMOS process, achieving 2TOPs/W energy efficiency with 34fps throughput under VGA-resolution output for real-time LiDAR systems.

This article presents a gallium nitride (GaN) wideband millimeter-wave power amplifier (PA) incorporating the Chebyshev matching technique. The theoretical design method of the wideband $N$ -order Chebyshev matching network is proposed. Considering the insertion loss and circuit complexity, the second-order Chebyshev network is designed, which is implemented by transmission lines (TLs) and capacitors. Based on the designed matching network, a $K$ -band PA is designed. Fabricated in a 250-nm GaN process, our PA scores the highest in-band gain of 23.8 dB at 23.6 GHz, 28% fractional bandwidth across 18.5–24.5 GHz, 32% peak power added efficiency (PAE), and 4.5-W saturated output power. The power density is 0.96 W/mm2 and the chip area is $2.4\times1.95$ mm2.

In this paper, a millimeter-wave broadband high-efficiency power amplifier (PA) for Ka-band (26-32 GHz) using 0.15-& mu;m GaAs pseudomorphic high-electron-mobility transistor process is proposed. The PA utilizes a three-stage cascade structure and adopts an RC series feedback network, which expands the bandwidth and ensures the circuit stability. To improve the output power and efficiency of the circuit, a tree-like transistor structure is proposed. The power amplifier, it can provide 23.6 dBm output P-1dB with 33.1% power-added efficiency at 28 GHz with high linearity. The maximum small signal gain can reach 27 dB with 3-dB bandwidth from 24 to 33 GHz for the measured results.

Summary In this paper, a broadband superheterodyne receiver (RX) front‐end for millimeter‐wave (mm‐Wave) imaging radar is presented. Realized in 28‐nm CMOS technology, the proposed RX incorporates a wideband low‐noise amplifier (LNA), double‐balanced passive mixers for the dual down‐conversion, a differential power divider, a differential intermediate frequency filters, a current‐mode‐logic divider‐by‐2, and a local oscillator buffers. Wideband technique and layout optimization are taken into consideration in the RX. A four‐stage LNA is devised to realize the high gain and low noise figure (NF) with a common‐gate input stage and three pseudodifferential common‐source stages. Optimized transistor layout and capacitor neutralization technique are developed to improve gain and noise performance. Transformer‐based matching networks with the peak‐staggered technique are adopted in the LNA to achieve a flatter gain response with a wider bandwidth (BW). The passive double‐balanced mixers are implemented with a highly symmetrical layout for broadband down‐conversion. Simulation results show that the mm‐Wave RX front‐end exhibits a BW ranging from 90 to 115 GHz. The simulated NF of our RX is 4.7 dB at 86 GHz. With a supply voltage of 1 V, the presented RX consumes 88.2‐mW power and occupies a chip size of 1.6 × 0.5 mm 2 including all the testing pads. The proposed RX is suitable for W‐band imaging systems.

A design of 4-channel 12-bit Successive Approximation Register analog to digital converter (SAR ADC) is presented by this paper. The whole chip is composed by four sub-ADC cores for baseband application. Each individual core contains clock buffer, reference buffer and a programmable gain amplifier for input signals. In this work, A split-capacitor digital to analog converter (CDAC) for reducing the common mode voltage input swing in comparator. Considering the limited chip layout area, bridge structure was chosen for this design.

This paper presents a 10 bit 300MS/s single channel asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 28nm CMOS technology. The improved SAR logic shortens the logic path delay and leads more settling time for the capacitive digital-to-analog converter (CDAC) capacitor rollover. The ADC is designed in TSMC 28nm technology. It achieves SNDR/SFDR of 58.80 dB/81.9dB and 57.6 dB/79.0dB at low and Nyquist input frequency, respectively, resulting in figure of merit (FoM) of 11.3 fJ/conversion-step.