The BlueGene/L (BG/L) supercomputer is designed to deliver new levels of application performance by providing a combination of good single-node computational performance and high scalability. To achieve good single-node performance, the BG/L design includes a special dual floating-point unit on each processor and the ability to use two processors per node. BG/L also includes both a torus and a tree network to achieve high scalability. We demonstrate how benchmarks and applications can take advantage of these architectural features to get the most out of BG/L.Achieving high sustained application performance has been one of the chief goals of the BG/L project [1]. The BG/L system was designed to provide a very high density of compute nodes with a modest power requirement, using a low-frequency embedded system-on-a-chip technology. The BG/L compute node is targeted to operate at 700 MHz. To obtain good performance at this relatively low frequency, each node needs to process multiple instructions per clock cycle. This can be achieved through two main strategies. First, one can make use of both processors in each BG/L node. Second, each processor has a dual floating-point unit with fused multiply-add instructions, which can perform four operations per cycle using special SIMD-like instructions. We investigate two strategies for leveraging the two processors in each node: coprocessor mode and virtual node mode.