Since several years, classical multiprocessor systems have evolved to multicores, which tightly integrate multiple CPU cores on a single die or package. This technological shift leads to sharing of microarchitectural resources between the individual cores, which has direct implications on the performance of parallel applications. It consequently makes understanding and tuning these significantly harder, besides the already complex issues of parallel programming. In this work, we empirically analyze various microarchitectural effects on the performance of parallel applications, through repeatable experiments. We show their importance, besides the effects described by Amdahl's law and synchronization or communication considerations. In addition to the classification of shared resources into storage and bandwidth resources of Abel et al. [1], we view the physical temperature and power budget also as a shared resource. Dynamic Voltage and Frequency Scaling (DVFS) over a wide range is needed to meet these constraints in multicores, thus it is a very important factor for performance nowadays. Our work aims to gain a better understanding of performance-limiting factors in high performance multicores, it shall serve as a basis to avoid them and to find solutions to tune parallel applications.

Register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation as a first step without assuming a schedule lacks the information of interferences between values live ranges. Thus, the register allocator may introduce an excessive amount of false dependences that dramatically reduce the ILP (Instruction Level Parallelism). We present a new theoretical framework for controlling the register pressure before software pipelining. This is based on inserting some anti-dependence edges (register reuse edges) labeled with reuse distances, directly on the data dependence graph. In this new graph, we are able to fix the register pressure, measured as the number of simultaneously alive variables in any schedule. The determination of register and distance reuse is parameterized by the desired minimum initiation interval (MII) as well as by the register pressure constraints either can be minimized while the other one is fixed. After scheduling, register allocation is done on conventional register sets or on rotating register files. We give an optimal exact model, and an approximation that generalizes the Ning-Gao [22] buffer optimization method. We provide experimental results which show good improvement compared to [22]. Our theoretical model considers superscalar, VLIW and EPIC/IA64 processors.

Chapter 8 The Register Saturation Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Book Author(s):Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author First published: 07 May 2014 https://doi.org/10.1002/9781118625446.ch8 AboutPDFPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShareShare a linkShare onFacebookTwitterLinked InRedditWechat Summary This chapter shows how to handle the register pressure before the instruction scheduling of a data dependence graph (DDG). It provides a mathematical study to an approach that consists of managing the exact upper bound of the register need for all the valid schedules of a considered DDG, independently of the functional unit constraints. The aim of register saturation (RS) of the DDG is to detect possible obsolete register constraints. The RS concept aims to decouple register constraints from instruction scheduling without altering instruction-level parallelism (ILP) extraction. The chapter formally defines the RS in acyclic and cyclic scheduling, and provides efficient ways to compute it. It provides formal characterization of RS helping us to provide an efficient heuristics. The RS inside a DAG devoted to acyclic instruction scheduling is examined in the chapter; the notion is extended to loops devoted to software pipelining (SWP). Advanced Backend Code Optimization RelatedInformation

Free Access Appendix 7 Appendix of the Speedup-Test Protocol Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Book Author(s):Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author First published: 07 May 2014 https://doi.org/10.1002/9781118625446.app7 AboutPDFPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShareShare a linkShare onFacebookTwitterLinked InRedditWechat Advanced Backend Code Optimization RelatedInformation

Chapter 10 Exploiting the Register Access Delays Before Instruction Scheduling Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Book Author(s):Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author First published: 07 May 2014 https://doi.org/10.1002/9781118625446.ch10 AboutPDFPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShareShare a linkShare onFacebookTwitterLinked InRedditWechat Summary This chapter is related to the problem of periodic scheduling with register requirement optimization; its aim is to solve the practical problem of register optimization in optimizing compilation. The exploitation of register access delay means the usage of non-positive edges latencies in a data dependence graph (DDG). The DDG circuits with non-positive distances may prohibit periodic instruction scheduling under resource constraints from finding a solution, making the compilation process to fail. The chapter shows how to avoid the problem in the schedule independent register allocation (SIRA) framework. It explains the problem that results if we insert non-positive edges inside DDG. The chapter studies a sufficient and necessary condition that defines a DDG without non-positive circuits. The chapter summarizes experimental results and draws comparisons between the efficiency of the reactive and proactive methods. Advanced Backend Code Optimization RelatedInformation

Introduction xiii Part 1 Prolog: Optimizing Compilation 1 Chapter 1 On the Decidability of Phase Ordering in Optimizing Compilation 3 Part 2 Instruction Scheduling 23 Chapter 2 Instruction Scheduling Problems and Overview 25 Chapter 3 Applications of Machine Scheduling to Instruction Scheduling 39 Chapter 4 Instruction Scheduling Before Register Allocation 51 Chapter 5 Instruction Scheduling After Register Allocation 77 Chapter 6 Dealing in Practice with Memory Hierarchy Effects and Instruction Level Parallelism 91 Part 3 Register Optimization 119 Chapter 7 The Register Need of a Fixed Instruction Schedule 121 Chapter 8 The Register Saturation 141 Chapter 9 Spill Code Reduction 159 Chapter 10 Exploiting the Register Access Delays Before Instruction Scheduling 177 Chapter 11 Loop Unrolling Degree Minimization for Periodic Register Allocation 191 Part 4 Epilog: Performance, Open Problems 231 Chapter 12 Statistical Performance Analysis: The Speedup-Test Protocol 233 Conclusion 257 Appendix 1 Presentation of the Benchmarks Used in Our Experiments 263 Appendix 2 Register Saturation Computation on Stand-Alone DDG 271 Appendix 3 Efficiency of SIRA on the Benchmarks 279 Appendix 4 Efficiency of Non-Positive Circuit Elimination in the SIRA Framework 293 Appendix 5 Loop Unroll Degree Minimization: Experimental Results 303 Appendix 6 Experimental Efficiency of Software Data Preloading and Prefetching for Embedded VLIW 313 Appendix 7 Appendix of the Speedup-Test Protocol 319 Bibliography 327 Lists of Figures, Tables and Algorithms 345 Index 353

The chapter provides the memory disambiguation mechanisms in some high-performance processors. Such mechanisms, coupled with load/store queues in out-of-order processors, are crucial to improving the exploitation of instruction-level parallelism (ILP), especially for memory-bound scientific codes. The chapter discusses the cache effects optimization at instruction level for embedded very long instruction word (VLIW) processors. The introduction of caches inside processors provides micro-architectural ways to reduce the memory gap by tolerating long memory access delays. The chapter presents a backend code optimization for tolerating non-blocking cache effects at the instruction level. It shows how to study the dynamic behavior of memory request processing, and provides examples on three superscalar processors. The chapter describes the aspect of memory hierarchy, which is cache misses penalties. It presents a method to reduce processor stalls due to cache misses in presence of non-blocking cache architectures.

Chapter 5 Instruction Scheduling After Register Allocation Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Book Author(s):Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author First published: 07 May 2014 https://doi.org/10.1002/9781118625446.ch5 AboutPDFPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShareShare a linkShare onFacebookTwitterLinked InRedditWechat Summary This chapter presents a postpass instruction scheduling technique suitable for just-in-time (JIT) compilers targeted to VLIW processors. Just-in-time (JIT) compilation of programs distributed as Java or .NET Common Language Infrastructure (CLI) byte-codes are becoming increasingly relevant for consumer electronics applications. The chapter proves that the new postpass instruction scheduling preserves the instruction schedules created by prepass scheduling and software pipelining, provided that register allocation and basic block alignment only introduced redundant scheduling constraints. It reviews local instruction scheduling heuristics and propose scoreboard scheduling. The chapter then describes an optimized implementation of the technique. In addition, it discusses inter-region instruction scheduling and introduces inter-block scoreboard scheduling. This technique relies on iterative scheduling constraint propagation. Finally, the chapter provides an experimental evaluation of the contributions, which are implemented in the STMicroelectronics CLI-JIT compiler that targets the ST200 VLIW and the ARM processors. Advanced Backend Code Optimization RelatedInformation

Free Access Appendix 4 Efficiency of Non-Positive Circuit Elimination in the SIRA Framework Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author Book Author(s):Sid Touati, Sid TouatiSearch for more papers by this authorBenoit Dupont de Dinechin, Benoit Dupont de DinechinSearch for more papers by this author First published: 07 May 2014 https://doi.org/10.1002/9781118625446.app4 AboutPDFPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShareShare a linkShare onFacebookTwitterLinked InRedditWechat Advanced Backend Code Optimization RelatedInformation