several design challenges of a low pass continuous time delta sigma modulator (LP DSM), to be used in switched mode transmitter architecture, have been identified. MATLAB simulations and modulation schemes for LP DSM have been presented. Various analog issues, mainly concerned with loop filter design, are discussed. Finally a highly efficient switched mode transmitter architecture using delta-sigma modulation and class-D amplifier is implemented. The transmitter architecture is operated at 200MHz.

This paper presents the design and FPGA implementation of a 2 nd order all-digital Adaptive Delta Sigma (∆∑) modulator with one bit quantization. It has a modulator stage and an adaptation stage. The adaptation stage produces a feedback signal that tracks the input signal and is subtracted from it. This difference signal is in a controlled and reduced range. It is given to the input of the modulator stage which has a 2 nd order ∆∑ modulator. This results in a reduction of quantization noise and an increase in the overall Signal to Quantization Noise Ratio (SQNR) of the modulator. The design was implemented on a Xilinx Spartan family FPGA using the Xilinx System Generator for DSP tool. The Hardware Co-Simulation mode of the System Generator was used which enables Simulink to run the FPGA directly, thus facilitating extensive testing. The spectral and SQNR analysis of the FPGA output was performed in MATLAB. The 2 nd order adaptive ∆∑ modulator presented here, exhibits an average SQNR improvement of 24.66 dB, 22.11 dB, 16.59 dB and 8.24 dB over the 2 nd order non-adaptive ∆∑ modulator at Over Sampling Ratios (OSRs) of 512, 256, 128 and 64 respectively in an input power range of -80 to 20 dB. It also exhibits an increased dynamic range of approximately 24 dB over the 2 nd order non-adaptive ∆∑ modulator.