The authors developed and made use of the microDAC deformation measurement technique to determine strain fields on thermally stressed, cross sectioned FC and CSP specimens. The method allows one to resolve strain fields inside tiny structures like e.g. solder interconnects or conductive adhesive layers. It is based on comparison of digitized micrographs obtained from different object load states. Optical, SEM and laser scanning microscopy are applied for image capture. The paper presents results of strain analysis in interconnects of different flip chip configurations and chip scale package types e.g., global shear of outward bumps is almost completely suppressed in most flip chip cases by underfilling. Furthermore, bump deformation can be strongly influenced by the local appearance of glass fabrics in organic laminates used as board materials. A main demand on chip scale package reliability is the avoidance of too large thermal solder ball strains, which lead to material fatigue. Different packages with rigid and flex interposers tackle the stress compensation problem in a different way. A first attempt is made to compare some of them based on experimental strain and warpage measurements

Developing a CSP at waferlevel is a challenging task with respect to board level reliability. Board level reliability should be achieved in contrast to flip chip technology without underfilling. Of course the target of a CSP manufacturing technology at waferlevel is cost reduction.The S-3-Diepack is a waferlevel CSP developed at the Technical University of Berlin within the European ESPRIT project ESCHETA. The S-3-Diepack uses a redistribution layer to a achieve a standardized I/O-array and stacked solder spheres with a solder support structure (S-3) to improve board level reliability.The S-3-Diepack used in this investigation has a size of 10 mm x 10 mm, 196 I/O's and a pitch of 0.5 mm. Due to the stacked solder spheres a stand-off height of about 0.4 mm is achieved after assembly. 1000 cycles - 40 to + 100 OC have been achieved on a thin FR5 board before electrical failure. Over 750 cycles - 55 to + 125 degrees C were passed on thick FR4 board.

The thermo-mechanical reliability of chip scale packages (CSP) is determined by the package technology as the package has to compensate the thermal mismatch between the silicon die and the substrate. In contrast to flip chip technology the CSP is usually assembled on the printed circuit board without underfilling. Nonlinear Finite Element Analysis has been performed to compare different CSP approaches under thermal cyclic load and to allow a life time estimation with respect to the various geometric design parameters and to the complex mechanical behavior of the materials used. Numerical simulation has been used to support CSP development and to classify different types of CSP according to their reliability.