The thermoelectric properties of doped polycrystalline silicon nanowires have been investigated using doping techniques that impact grain growth in different ways during the doping process. In particular, As- and P-doped nanowires were fabricated using a process flow which enables the manufacturing of surface micromachined nanowires contacted by Al/Si pads in a four-terminal configuration for thermal conductivity measurement. Also, dedicated structures for the measurement of the Seebeck coefficient and electrical resistivity were prepared. In this way, the thermoelectric figure of merit of the nanowires could be evaluated. The As-doped nanowires were heavily doped by thermal doping from spin-on-dopant sources, whereas predeposition from POCl3 was utilized for the P-doped nanowires. The thermal conductivity measured on the nanowires appeared to depend on the doping type. The P-doped nanowires showed, for comparable cross-sections, higher thermal conductivity values than As-doped nanowires, most probably because of their finer grain texture, resulting from the inhibition effect that such doping elements have on grain growth during high-temperature annealing.

Dimensional confinement in silicon nanowires (NWs) is well-known for enhancing phonon scattering, thus leading to a pronounced reduction of thermal conductivity κ with respect to bulk material. The effect of confinement on phonon scattering in nanolayers (NLs), however, has not been fully understood. In this work, thermal conductivity on polycrystalline silicon NLs with roughened surfaces and thicknesses ranging from 30 to 100 nm has been experimentally investigated. For measurement purposes, the nanostructures were fabricated with a dedicated surface nano-machining process, thus producing vertical silicon nanostructures suspended on Al/Si electrodes on a silicon substrate, using SiO2 as a sacrificial layer. By designing such structures in a four-terminal configuration, their κ could be determined by the current-voltage method. Boron doped silicon NLs were examined, at resistivity ranging between 2 and 10 m\(\Upomega\) cm. We found an increase of phonon scattering from the confinement, since κ decreased steadily with the thickness from values typical of thick films (around 30 W m−1 K−1) down to <15 W m−1 K−1. Compared to NWs, NLs had displayed figures of merit smaller by one order of magnitude. However, due to the larger filling factor, they were able of generating more than five times the electric power per area unit that could be obtained with high-density stacks of top-efficiency NWs.

Comparative studies of gate oxides on a N+ pre-implanted area (Ninterface ~1x1019cm-3) and on a virgin Si face 4H-SiC material (Ninterface ~1x1016cm-3) have been undertaken by means of Capacitance-Voltage (C-V) characteristics, performed at different temperatures and frequencies, and Thermal Dielectric Relaxation Current technique. In the non implanted samples, the stretch out of the C-V curves get larger as the temperature is lowered to 150K, while for lower temperatures the C-V characteristics become steeper and some discontinuities occur. These discontinuities are specific for the non-implanted sample and are associated with charging of the fast near interface states (NIToxfast) via a tunneling from the shallow interface states (Dit). The tunneling from the shallow Dit to NIToxfast supress the a.c. response of Dit, which is recovered only after most of the NIToxfast are charged with electrons.

An experimental investigation about the thermoelectric properties of heavily doped p ad n-type nanocrystalline silicon nanowires (NWs) is described. The NWs are produced with low cost CMOS compatible processes, highly customizable in terms of cross-section and placement, which enables the fabrication of both stacked NWs in nearly vertical arrays within nanostructured templates built with SiO2/Si3N4 thin films and individual, freestanding NWs suited for thermal conductivity measurements. The cross-section dimensions of the investigated NWs range between 30 and 120 nm in size and up to about 2 cm in length. The structure of the NWs, as shown by SEM/TEM observations, is nanocrystalline with average size of the nanocrystals in one dimension that is comparable with the nanowire diameter. On the NWs, Seebeck coefficient, electrical resistivity and thermal conductivity have been measured, yielding thermoelectric figure of merit (ZT) values of 0.2 at 300 K for the best case.

The effect of nitrogen (N) introduced by ion implantation at the SiO2/4H-SiC interface on the capacitance of the MOS capacitors is investigated. The Thermal Dielectric Relaxation Current (TDRC) technique and Capacitance-Voltage (C-V) measurements performed at different temperatures and probe frequencies on an N implanted sample and on a virgin sample were employed for this purpose. There are three types of defects located at or near the interface, D-it, NIToxfast and NIToxslow that can be distinguished. Only D-it and NIToxfast respond to the a.c. small, high frequency signal at temperatures above 150K. The separation of D-it from the NIToxfast states have enabled us to study the influence of the excess of interfacial Nitrogen on each of the mentioned defects. It has been found that the N-implantation process fully suppresses the formation of NIToxfast and partially NIToxslow and D-it. Theoretical C-V characteristics were computed, based on the defect distributions determined by TDRC, and compared with the experimental ones showing a close agreement.

As far as the fabrication of ultradense crossbars is related to correspondingly dense wire arrays, the crossbar route to tera-scale integration depends on the availability of preparation techniques for wire arrays with density of 10(6) cm(-1) or more. For a planar arrangement this density implies a pitch of 10 nm or less, beyond the current possibility and close to the theoretical limit, assuming for the cross-point a minimum area of 10 nm(2). Further increase of density can only be achieved organizing the nanowires in a three-dimensional fashion. This paper describes a planar top-down process for the preparation of vertically arranged poly-silicon nanowires. The technique is expected to allow the production of wire arrays with linear density (projected on the surface) larger than those achievable with any other proposed top-down processes. Used for the fabrication of the bottom wire array of crossbars, this process should allow an eventual cross-point density of the order of 10(12) cm(-2), thus being a candidate technology for tera-scale integration.

The codiffusion of B and Sb implanted in Si with a dose of 2 × 1016 cm−2, corresponding to concentration far above the solid solubility, is investigated at 900 and 1000 °C on the basis of SIMS and carrier profile measurements and TEM observations. The comparison of the codiffusion data with the corresponding ones obtained by the diffusion of each element alone revealed several anomalous effects due to dopant interaction. In particular, our experimental results support the hypothesis of the formation of mobile donor-acceptor pairs and of the increase of the Sb solubility in the region where a high concentration of acceptors is present. On the basis of this feature, a diffusion model that takes pairing and precipitation into account is presented. A simulation program including this model allows us to foresee most of the anomalous phenomena occurring in the high concentration codiffusion experiments and shows in general a satisfactory agreement with experimental profiles.

A process is developed for the fabrication of vertically arranged poly-silicon nanowires via a rigorously top-down batch process. The technique allows the production of wire arrays with larger linear density (projected on the surface) than those achievable with any of the other proposed top-down processes.

The precipitation of P in the emitter region of H3PO4 spray doped silicon for solar cell applications has been investigated by electron microscopy, X-ray microanalysis and electrical measurements after annealing for two different times. P, Si and O concentration profiles show that the composition of the phosphorous silicate glass (PSG) is in agreement with a solid solution of P2O5 in SiO2 and that P concentration is peaked at the PSG/Si interface. TEM observations have shown for the shorter annealing the formation of a 20nm thick defect layer at the silicon surface; this layer evolves into a network of large rod-like monoclinic (or orthorhombic) SiP precipitates, which extend in depth up to about 100nm for the longer treatment. The SiP crystal structure and the habit planes are the same as previously reported in literature. No deeper defect that could interact with the junction located at about 300nm has been detected. Although the SiP precipitation takes place entirely at the Si surface, it is not significantly affected by the orientation of the crystals and by the texturing process. The amounts of both electrically active and inactive P obtained by the H3PO4 spray technique have been compared with the ones obtained by the conventional POCl3 technique. The former process presents a larger amount of inactive dopant, a finding that is in keeping with the microstructural and microanalytical observations. Instead the amount of active P is similar in the two cases, a result attributed to the precipitation and clustering phenomena of the excess dopant.

Structural, morphological and electrical characteristics of Al-implanted p+/n 4H-SiC diodes are compared for the same implantation process and post implantation annealing with identical stationary and cooling cycles but different heating rate. Al+ ions were implanted at 400°C, with energies in the range 250–350 keV and 1.2 × 1015 cm−2 fluence. Post implantation annealing processes were done at 1600°C for 30 min with a constant heating rate in the range 7–40°C/s and an abrupt cooling cycle. Gas in the annealing ambient was high purity Ar. The Al depth profile of annealed and as implanted samples were equal except for concentrations below 1017 cm−3 where the former profiles showed a diffusion tail. With the increase of the heating rate of the post implantation annealing process, the sheet resistance of the Al implanted layer and diode leakage current decrease while the surface roughness increases.

This study compares p-MOS capacitors fabricated on N+ implanted and on virgin 4H-SiC. The former sample have N at the SiO2/SiC interface, the latter have not. To investigate the presence of deep and shallow hole traps at the SiO2/SiC interface, high frequency and quasi-static capacitance voltage measurements under dark have been compared for bias sweeping from accumulation to depletion and from depletion to accumulation, the latter after white light illumination. The presence of N has an effect on the density of the shallow donor like traps but none effect on the deep ones. The positive charge trapped in the oxide and/or at the oxide interface after equivalent tunneling hole injection have been compared and are equivalent. Time dependent dielectric breakdown tests have been compared too. The oxide grown on N+implanted SiC broken at lower electric field.

The electrical characteristics of n-metal oxide semiconductor field effect transistors (n-MOSFETs) fabricated on 4H-SiC with a process based on nitrogen (N) implantation in the channel region before the growth of the gate oxide are reported as a function of the N concentration at the SiO2/SiC interface. A strong correlation among the increase in the N concentration, the reduction of the interface state density near the conduction band and the improvement of the MOSFET performance was obtained. Hall-effect measurements were used to determine the electron mobility and the free carrier concentration in the MOSFET channel. Among the investigated combinations of N dose and oxidation time, the one with the higher dose and the shorter time produces MOSFETs with the higher N concentration at the SiO2/SiC interface and the best electrical characteristics. This superior performance is obtained in spite of the lowering of the bulk mobility in the channel of this sample, a negative effect probably ascribable to the incomplete recovery of the implantation damage or to the high density of interstitial nitrogen atoms present in the channel region. However, evidence of extended defects, clusters or nanoparticles was not observed by transmission electron microscopy analyses in any of the investigated SiC MOSFET devices.

The race of integrated-circuit technology towards high bit density has already brought transistor densities of the order of 10(9) cm(-2), while keeping conventional circuit layouts. Crossbar structures are widely believed to meet the requirements of high bit density along with sustainable interconnection complexity avoiding the dramatic cost increase of the manufacturing facilities required by advanced lithography. In this work we demonstrate the possibility of producing poly-Si nanowires preserving bulk electrical properties that are nonetheless so dense as to allow cross-point density in excess of 10(11) cm(-2). This result could be achieved by organizing silicon nanowires in nearly vertical arrays.

The observation that the thermal conductivity of single-crystalline silicon nanowires with diameter on the length scale of 25 nm is lower than that of bulk material by two orders of magnitude has attracted the interest onto silicon as a potentially effective thermoelectric material. However, the potential interest has a hope of transforming in a practical interest only if poly-crystalline silicon can replace single crystalline silicon and the preparation of nanowires does not involve any advanced photolithography. In this work we show that a technique, based on the controlled etching and filling of recessed regions and employing standard photolithography and deposition-etching methods, succeeds in the preparation of poly-crystalline silicon nanowires (with diameter of 25 nm and length on the centimetre scale) at a linear density of 3E6 cm^-1.

In this paper the electrical and structural characteristics of n-MOSFETs fabricated on 4H SiC with a process based on nitrogen (N) implantation in the channel region before the growth of the gate oxide are reported for low (5x1018 cm-3) and high (6x1019 cm-3) N concentration at the SiO2/SiC interface. The electron mobility and the free carrier concentration in the MOSFET channel were evaluated by Hall effect measurement. The MOSFETs with the higher N concentration had the best electrical characteristics in terms of threshold voltage and field effect mobility, in spite of a lowering of the electron mobility in the channel. The latter is a negative drawback of the fabrication process that probably can be ascribed to an incomplete recovery of the implantation damage or to a high density of interstitial N atoms present in the channel region. In fact, the MOSFETs with the superior electrical performances were fabricated with the higher N+ dose and the shorter thermal oxidation time. However, no evidence of extended defects, clusters or nano-particles in SiC at the interface with the gate oxide was found in every SiC MOSFETs devices observed by electron transmission microscopy

Electron states at the SiO2/4H–SiC interface have been investigated using capacitor structures and especially, the influence of excess nitrogen, introduced by ion implantation, at the interface is studied in detail. Implanted and nonimplanted n-type samples with an interfacial concentration of nitrogen of ∼1019 cm−3 and 1016 cm−3, respectively, were analyzed by capacitance-voltage (C-V) measurements, performed at different temperatures and probe frequencies, and thermal dielectric relaxation current (TDRC) measurements performed in the temperature range of 35–295 K. Three main categories of electron states are disclosed, true interface states (Dit), fast near interface states (NIToxfast) and slow near interface states (NIToxslow). The density versus energy distributions of Dit and NIToxfast have been deduced from the TDRC data and they are shown to give a close quantitative agreement with the shape and frequency dependence of the C-V curves. Further, the amount of NIToxslow extracted from TDRC is demonstrated to be responsible for the parallel shifts and hysterezis effects occurring in the C-V characteristics. All three categories of electron states are reduced in concentration in the implanted samples. This holds particularly for NIToxfast with a peak at ∼0.1 eV below the conduction band edge of 4H–SiC that is suppressed by at least two orders of magnitude relative to the nonimplanted samples. The decrease for Dit is also substantial (a factor of ∼10) while the loss for NIToxslow is considerably smaller (only ∼30%). The results provide firm evidence that NIToxfast and NIToxslow do not originate from the same kind of defect center.

Phosphorous implanted n+/p diodes have been included in the masks for manufacturing n-MOSFET devices and processed in the same way of source/drain regions. The diode junctions were made by a P+ implantation at 300°C and a post implantation annealing at 1300°C. The diode emitter area was protected by 0.6 m thick CVD oxide during the processing of the MOSFET gate oxide. Three gate oxide processes were taken into account: two of them include a N implantation before a wet oxidation, while the third one was a standard oxidation. Considering the effect on the n+/p diodes, the main difference among the processes were the wet thermal oxidation time that ranged between 180 and 480 min at a temperature of 1100°C. The diode current-voltage characteristics show similar forward but different reverse curves in the temperature range of 25-290°C. Differences in reverse bias voltage as a function of the measurement temperature have been analyzed and are related to the different gate oxidation time. A correlation between the shortest oxidation time and the lower leakage current is presented.

The electrical characteristics of MOSFETs fabricated on 4H-SiC with a process based on N implantation in the channel region before the growth of the gate oxide are reported as a function of the N concentration at the SiO2/SiC interface up to 6  1019 cm-3. The field effect mobility improves with increasing N concentration. At room temperature values change from 4 cm2/Vs for the not implanted sample up to 42 cm2/Vs for the sample with the highest N concentration. Furthermore, the field effect mobility increases with temperature and presents values above 60 cm2/Vs at 200 °C. The MOSFETs with the better electrical characteristics (higher mobility, lower threshold voltage, lower subthreshold swing) were fabricated by a low thermal budget oxidation process, thank to the use of a high N implantation dose able to produce an amorphous SiC surface layer. A strong correlation among the increasing of the N concentration at the SiO2/SiC interface, the reduction of the interface state density located near the conduction band and the improvement of the MOSFETs performance was obtained.

This work is focusing on the effect of a high concentration of nitrogen (N) introduced by ion implantation at the SiO2/4H-SiC interface in MOS capacitors. The N implanted sample (Ninterface ~1x1019cm-3) is compared with a non-implanted one (Ninterface ~1x1016cm-3) by means of the electron interface trap density (Dit). The Dit is determined via High-Low frequency C-V method and Thermal Dielectric Relaxation Current (TDRC) technique. It is shown that the TDRC method, mainly used so far for determination of near interface oxide charges, can be exploited to gain information about the Dit too. The determined value of Dit in the N-implanted sample is nearly one order of magnitude lower than that in the sample without N implantation. Good agreement between the TDRC results and those obtained from High-Low frequency C-V measurements is obtained. Furthermore, the TDRC method shows a high accuracy and resolution of Dit evaluation in the region close to the majority carrier band edge and gives information about the traps located into the oxide.

We report investigations on the fabrication and electrical characterization in the range 27°C -290 °C of normally off 4H-SiC circular MOSFET devices manufactured on p-type semiconductor. An high quality SiO2/SiC interface is obtained by nitrogen ion implantation conducted before the thermal oxidation of SiC. Two samples with different nitrogen concentration at the SiO2/SiC interface and one un-implanted have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. With increasing temperature, in all the samples the threshold voltage decreases and the electron channel mobility increases, reaching the maximum value of about 40 cm2/Vs at 290 °C for the sample with the highest N concentration. The observed improvement of the mobility is related to the beneficial effect of the N presence at the SiO2/SiC interface, which leads to the reduction of the interface trap density with energy close to the conduction band. Our results demonstrate that N implantation can effectively be used to improve the electrical performance of surface n-channel 4H-SiC MOSFETs.