Circuit sizing of analogue building blocks is often still done by hand. Experts in circuit design are not necessarily experts in computer science and programming. Thus, it is not easy to find scripts providing automated sizing procedures. In this work, a Python framework is presented, simplifying the use of analogue design automation. It provides a tool- and technology agnostic approach and is explicitly developed with focus on circuit design. Therefore, the entry barrier is kept as low as possible. The framework supports an “agile” approach for developing new ideas interactively as well as a “waterfall” mode to simplify sequential design tasks. But describing e.g. iterations in a script, as designers do in their sizing process manually, makes re-use possible. With very little extra effort, re-use for multiple MOS technologies can be enabled as well. The idea is not to replace design engineers, but to increase design efficiency and improve re-use within and across technologies and design communities, by simple to read and use executable notebooks. Later, such notebooks can be collected in asset classes. This is demonstrated using simple examples.

In this paper, a carrier recovery technique based on the concept of dual loop regenerative LO signal is proposed. The recovery core involves a novel multi-phase 4xsub-harmonic mixer based regenerative divider followed by a PLL block. The focus of this receiver is to regenerate the LO signal from the input pilot tone and make the PLL stay in lock with the recovered LO during the multitone input without degrading the overall SNR. The proposed concept alleviates the problem of conventional regenerative divider which suffers from degradation of SNR for muti tone input signal. To test the proof of concept the proposed method is investigated through the circuit level simulations and verilogA model of PLL and the feasibility is examined via the successful down-conversion of the modulated data with the regenerated LO signal with a significant SNR. The proposed carrier recovery receiver is implemented in 28nm CMOS process and simulated for the RF pilot tone of frequency 28GHz and multitone signal bandwidth of 200MHz. The novelty of this method is, it can be used for the receiver working at higher frequencies relaxing the requirements of LO to 1/5(th) (5.6GHz)of the incoming signal frequency.

Analog circuit design automation remains an intense area of attention and has seen both new and existing tools continuing to be developed and targeting different phases of the analog design flow to reduce development time and cost. One of the promising tools is the Berkeley Analog Generator (BAG2) framework which is an open-source analog layout generator for automating and verifying circuit layouts. It promises a process-independent flow and it encourages design reuse due to using parameterized generators which can be scaled as required. This reduces the layout development time compared to manual handmade layouts. This work describes the effort and results of evaluating the BAG2 framework for the TSMC 65 nm and Cadence GPDK 45 nm processes. A case study is made with a number of circuits to discuss the problems in setting up and using BAG2 for the above technologies as well as the limitations and solutions required to utilize the framework effectively.

Circuit design automation is of great importance for modern electronics, enabling rapid prototyping and optimisation of analog circuits. This work exemplifies the application of the CUAS Cell Creator (CCC) framework based on Python language along with the g(m)/I-D method and precomputed look-up tables for automating the design of analog circuits with a specific focus on high speed dynamic comparators. To achieve the highly demanding specifications in terms of comparator speed and offset many design iterations are necessary, in which every step is traditionally done manually by the analog designer modifying the MOS transistor sizing, until the desired performance is achieved. Describing the circuit functionality using the classical Kirchoff equations together with unified treatment of all the regions of operation of the MOS transistor using g(m)/I-D method, provides an efficient way for design automation and reuse.

Analog circuit design automation remains an intense area of attention and has seen both new and existing tools continued to be developed targeting different phases of the analog design flow to reduce development time and cost. One of the promising tools is the Berkeley analog generator (BAG2) framework which is an open-source analog layout generator for automating and verifying circuit layouts. It promises a process-independent flow as well as encourages design re-use due to using parameterized generators which can be scaled as required and this reduces the layout-development time compared to manual hand-made layouts. This work describes the effort and results of evaluating the BAG2 framework for the TSMC 65nm and Cadence GPDK 45nm processes. A case study is made with a number of circuits to discuss the problems in setting up and using BAG2 for the above technologies as well as the limitations and solutions required to utilize the framework effectively.

In this work, the design of a multipath $3k^{th}(k\in N)$ harmonic rejection bandpass filter with tunable bandwidth and center frequency is proposed. The proposed filter architecture employs a nested filter structure with tunable non-identical loads in each filter to achieve the overall $3k^{th}$ harmonic rejection. This architecture also alleviates the need of an additional harmonic weighting stage to achieve an improved harmonic rejection. Six phase non-overlapping scheme is utlized to control the center frequency of a six path differential nested filter structure. The proposed harmonic rejection filter implemented in 28-nm is functional from the frequency range of 500 MHz to 2.9 GHz with channel bandwith tunable from 20 – 200 MHz. The overall harmonic rejection achieved at 1 G Hz is 58.6 dB. The achieved in-band $IIP_{3}$ is −14 dBm and noise figure is 6–8 dB in the entire frequency band.

This paper presents a design procedure that involves incorporating the parasitics into the design of a transformer based Matching Network(MN). In this work, flip-chip based integration is opted to connect the on-chip blocks to the external circuitry. At mm-Wave range, parasitics from the bump, ESD and metal traces play a vital role in altering the desired performance of MN. The inductance and capacitance contributed by the ESD structure and the flip-chip bump are extracted from EM simulations which are embedded into the design. This optimization process requires multiple trails which is addressed by SKILL code based spiral inductor layout generation. The MN designed in 28nm CMOS converts a 50Ω load to 4 + 5.1j for a mm-Wave DAC functioning at 28GHz.

In this work, a novel on-chip spectrum analyzer architecture is proposed based on the principle of Miller regenerative frequency dividers. The integrated spectrum analyzer implementation is challenging due to the high Q on-chip filtering requirement and complex down-conversion architecture. The proposed architecture utilizes a frequency divider for second stage down-conversion without the need for external local oscillator signal, thus resulting in a less complex overall architecture. Moreover, thanks to the proposed architecture, the challenge of down-converting wideband modulated input signal in frequency divider architectures is alleviated. The proposed spectrum analyzer architecture is simulated for three test input signals from 2 GHz to 3 GHz with minimum frequency resolution of 1 MHz, input dynamic range of 40 dB and minimum signal level of - 41 dBm. The radio frequency input signal is downconverted to 125 MHz at the analog output of the spectrum analyzer with the good Spurious-free dynamic range (SFDR) of 43 dB.

This paper presents a design procedure for implementation of a matching network with spurious tones rejection using on-chip transformer for high speed DAC applications. Such circuits are complex to analyze and design, due to the higher order of the network. The presented design procedure involves matching the impedance at a desired center frequency based on the input impedance equation and with the aid of mathematical computational platform to avoid tedious mathematical derivations. A test case is considered with center frequency of 28GHz and detectable spurious tones at 30GHz and 26GHz to verify the proposed design procedure. The designed network matches a 50Ω load to a complex impedance of 12-j5.3 and simultaneously rejects the spurious tones by imposing notch filter at 30GHz and suppressing the other tone at 26GHz by 9.5dB.

Summary form only given. The radiation exposure of electronic circuits and devices alters their electrical characteristics. When a high-energy particle hits a silicon substrate, and due to coulombian interaction, hole-electron pairs are created. A fraction of these carriers recombine but most of them are swept by the electric field in the depletion regions, generating current pulses that disrupt the normal operation of the circuit. As a consequence, this may lead to a very serious system failures, or progressive performance degradation. When critical missions use these systems, reliability is the main concern, therefore circuits with special considerations must be constructed using techniques for improving radiation tolerance as Radiation Hardening by Design (RHBD) that is cheap and fits well for designs implemented in sub-micron CMOS processes. To check circuit vulnerability of a hardened device different radiation tests must be conducted. For particle interaction tests, one of the most challenging tasks is to perform radiation ground tests that mimics real operation situations. Recently, many efforts have been achieved using laser equipments as in the works of Schwank1 and Palomo2 for transient fault injection, even though, the results must be correlated to heavy ion interaction to validate the approach. In this work, irradiation experiments with heavy-ions in VLSI circuits are reported. We explain how to lower the number of particles per second that reach the circuit, as also to focus the ion beam and control its position to hit on the desired place. We describe the dosimetry as also the measurement methodology. This work demonstrates that the use of a micro-beam line attached to a High-Energy accelerator is suitable for this kind of tests evidencing the validity and robustness of the method.

Testing of single event effects caused by heavy ions in a PLL implemented on a CMOS 90 nm technology is reported in this work. The diagnosis of the circuit vulnerability has been conducted with a heavy ion micro beam line facility at the TANDAR tandem accelerator facility. The accuracy of the positioning system has been evaluated and the radiation dose has been accurately characterized. Single event effects were induced in the circuit and a map of the spatial correlation for the most sensitive blocks has been obtained.

System and physical design of a dual core low power microcontroller based on an openMSP430 architecture is reported in this work. The system includes an on-chip program and data memory and a timer and a GPIO as peripherals. A top-down design flow has been followed using a digital standard cell library. The design has been manufactured on a commercial 180 nanometer high voltage technology node. The results of the followed design steps and simulation performance are given.

A simple approach for the design, fabrication and characterization of a operational trasconductance amplifier intended for work in low power applications is reported in this work. DC Measured parameters agree with simulation results and specifications. An application for the designed OTA is also tested.

The present paper reports the design and implementation of a system which purpose is the prevention of fires in forest areas. The system is based on the application of sensor networks, mobile telephony and data processing. Immediate availability of the values of different environmental variables and the application of several models, allow to assess the risk of fire in an area of interest very quickly. The system has been designed to ensure continuous operation, maximum reliability and minimum maintenance. The system has been developed by the Grupo de Investigacion en Sistemas Electronicos y Electromecatronicos (GISEE) of the Universidad Nacional del Sur. In the work we discuss the conception, design, and development of the system to arrive to a finished product.

A set of gates and registers was fabricated on a submicron CMOS process using radiation hardening by design techniques. The circuits were irradiated in a tandem accelerator with 10 MeV protons on three different doses. Off-line characterization of devices was carried out. Measurements showed minimum shifts on the electrical parameters of transistors. Noise margins and gain of combinational logic gates were unchanged and no increase on leakage current was observed. This work suggests that considerable tolerance to this kind of radiation damage can be reached when accurate design techniques are used together with modern integrated circuits technologies.

The present work contains information about the design and implementation of a SRAM memory that is able to cope with SEU and SET produced by radiation. This paper shows how two different techniques could be implemented together to aim that target. The architecture of the memory is proposed, and details of the different blocks are given. Also a new method is developed and proposed for automatic recovery of the data after a SEU. Making use of the proposed topics, an ASIC will be produced for diagnose and compare of the methods involved in the design.