Metal-semiconductor contact resistances are important for many semiconductor devices. They are often determined with the transmission line method (TLM). However, the 1-D analytic theory of the TLM only covers conducting layers that are thin when compared with the width of the line-shaped contacts. We report a 2-D analytic theory of the TLM that also applies to thick conducting layers. We demonstrate the correctness and necessity for using the 2-D analytical theory by comparing it to finite element simulations and to experimental data of samples that vary in thickness.

In this paper, we report and discuss several strategies to produce solar cell front contacts by full-area metallization and etching (FAME). Our chemically structured contacts consume less expensive silver than screen-printed contacts. As a proof of principle for the FAME approach, we present a 148.6-cm2-sized silicon solar cell that has about 100-μm-wide front-side fingers. These fingers consist of a 15-μm-thick evaporated aluminum layer, supplying the electrical conductance, and a sputtered capping stack (200 nm Ni:V plus 20 nm Ag), providing solderability. The entire metal stack is first deposited on the full area of the solar cells, then locally protected by a wax pattern, and subsequently etched with commercial Ni:V etch and NaOH. The efficiency of the best solar cell is 19.3%, the fill factor is 78%, the open-circuit voltage is 666 mV, and the short-circuit current density is 37.1 mA/cm2.

We demonstrate the module interconnection by means of screen printing. The metallization paste is printed over the edge of five heterojunction solar cells. This connects the frontside of a cell to an underlying Al-patterned rear-side contact of the neighboring cell. All cell interconnections are realized in a single printing step. Encapsulated modules reach open circuit voltages up to 683 mV per cell and designated area conversion efficiencies up to 17.0 %. The designated module area is 82 cm2. We eliminate shunts that originate from laser scribing to reach this efficiency. Quantitative dark lock in thermography images and I-V curve modeling of the shunting losses lead the way.

We investigate process sequences for obtaining solderable Al/Ni:V/Ag contacts to PERC-type crystalline Si solar cells by in-line Al evaporation. For a high cell efficiency the evaporated aluminum must be annealed at 350°C for about 5min. We find that annealing the Al/Ni:V/Ag metallization stack at temperatures above 150°C destroys the solderability of the wetting layer. A solution for this problem is to first deposit the 2.5μm Al layer by evaporation, then anneal the cell at 350°C for 10min, and finally sputter a double layer of Ni:V/Ag with respective thickness values of 200nm and 25nm. This process leads to a contact resistivity lower than 1 mΩcm2. The solderablility is proven by a peel force greater than 3N/mm. We present a solderable PERC cell with Al/Ni:V/Ag rear side metallization and an efficiency of 18.9%.

We present a study about loss analysis in both-sides-contacted silicon solar cells from a porous silicon (PSI) layer transfer process. Experimental results achieved by a variation of the rear-side contact geometry are characterized by different techniques such as electroluminescence and quantum efficiency measurements and reproduced by 3-D simulations using Sentaurus Device. Since such a device simulation does not include resistive losses in the metallization, we use a network simulation to account for losses caused by the grid. Considering the optimal contact geometry, the simulations indicate the power losses in the emitter, at the rear-side contacts, in the base, and in the metallization grid to be in the same order of magnitude.

We contact p-type wafers and boron-diffused layers by laser ablation of a passivating aluminum oxide and silicon nitride stack and subsequent in-line high-rate evaporation of aluminum. We measure saturation current densities at the base contacts of 2.5×106–1.9×107fA/cm2 for base resistivities of 0.5–3.8Ωcm and 491–905fA/cm2 for the contacts to boron-diffused layers of sheet resistances of 23–86Ω/sq. The contact resistivity of Al layers to p-type silicon with surface doping densities of 4×1015–3×1019cm−3 is in the range of 4–0.1mΩcm2, respectively. The measured contact properties allow for the fabrication of highly efficient ‘passivated emitter and rear cells’ (PERC) and ‘passivated emitter and rear totally diffused cells’ (PERT). Numerical simulations show that evaporated rear contacts in combination with screen printed contacts at the front allow for energy conversion efficiencies of 20.6% and of 21.1%, for PERC and PERT cells, respectively. The simulated free energy losses show that such cells are not limited by the in-line evaporated point contacts on the rear side.

We describe an open-source simulation tool for the modeling of photovoltaic devices with equivalent circuit networks. Our SpiceGUI interconnects devices with known current voltage characteristics and calculates the current density-voltage curve of the combined device. The SpiceGUI is written as hybrid Octave/MATLAB code and has a flexible graphical user interface. It supports batch simulations with the SPICE tools LTspice, NGspice, and SMARTspice. The available postprocessing functions include convenient batch parameter plots and power loss analysis diagrams. We present two simulation examples. The first example simulates a solar cell with front contact fingers. It assists the reader in understanding the SpiceGUI unit tree and serves as starting point for the development of custom models. This first example also shows that the SpiceGUI yields reliable results, even for very demanding models that exceed 4 GB working memory. The second example models back-contacted thin-film silicon solar cells. We use measured J(sc)-V-oc curves as input data for the current sources of the network. Additional resistive elements complete the network. The simulated JV curves of the combined device agree well with the measured JV curves. The distributed nature of the resistances is essential to describing the shape of the measured JV curves.

The literature describes various techniques for fabricating thin monocrystalline Si films without the need of sawing. Layer transfer using epitaxy on porous Si (PSI) and subsequent layer separation from the growth substrate is one particular attractive option. A 40 μm thick epitaxial Si cell from this so-called PSI process is capable of saving about 80 % of the Si that is consumed by a 180 μm-thick Si wafer plus 100 μm Si kerf loss. In addition, the two crystallizations of growing the poly-feedstock and of growing the ingot are replaced by a single crystallization: the epitaxial growth of a thin Si layer. Applying the PSI process, we demonstrate an independently confirmed aperture efficiency of 19.1 % for a 4 cm2-sized layer transfer cell that has a thickness of only 43 μm. This is the highest efficiency ever reported for a thin-film (<;50 μm) crystalline Si layer transfer cell. We achieve this record with a passivated emitter and rear contact (PERC) structure. The passivation layer is Al2O3 from atomic layer deposition (ALD). The contacts on the rear side are formed by laser ablation using ultrashort ps pulses (LCO). The ISFH roadmap that our PSI process development is a part of is also discussed in this contribution. Our program aims at developing thin-film/wafer hybrid technologies that shall combine the high efficiency potential of thin monocrystalline Si films with the low cost per area of the Si-thin-film world. 19%-efficient and less then 50 μm-thick layer transfer cells mark a large step forward towards the realization of such thin-film/wafer hybrid technologies.