We see an opportunity to improve overall performance by intelligently managing both the cache and prefetch using static structural information from program compilation during run-time. Such information enables better use of cache resources and promotes future-based (e.g., dependence graph lookahead) decisions on how to allocate resources rather than history-based (e.g., LRU replacement policy, branch history table). In this paper we outline the benefits of such a system and we verify the essential condition for enabling this approach: the existence of instruction run-lengths in applications that are necessary to support a sufficient level of prefetching. As evidence we present data showing the SPEC95 benchmarks from the persepective of instruction run-lengths.

Correctness in real-time computing depends on the logical result and the time when it is available. Real-time operating systems need to know the timing behavior of applications to ensure correct real-time system behavior. Thus, predictability in the underlying hardware operation is required. Unfortunately, standard, embedded cache management policies in microprocessors are designed for excellent probabilistic behavior but lack predictability, especially in a multitasking environment. In this article we examine the two popular cache management policies that support predictable cache behavior in a multitasking environment and quantitatively compare them. Using a novel application of an existing analytical cache model we show that neither policy is best in general and delimit the system characteristics where each is most effective.

Benchmarks and test suites are an essential element of the architectural evaluation process. At the conclusion of the last DARPA workshop on vision benchmarks to test the performance of parallel architectures, it was recommended that the DARPA Image Understanding Benchmark be extended with a second level task to add motion and tracking to the original task. We have now developed this new benchmark and a sample solution. This paper describes the benchmark, and presents some timing results for various common workstations.

Image segmentation is a fundamental operation in machine vision. This report explores the effectiveness of a Hopfield neural net for segmentation and improves on the basic algorithm with a region merging technique based on texture classification. Considerable empirical results show the effectiveness of the algorithm on complex real-world outdoor scenes. A detailed study is also made of porting the highly data parallel algorithm to the University of Massachuesetts-Amherst CAAPP layer of the Image Understanding Architecture, a bit serial SIMD parallel architecture.

In this document we describe the issues facing hardware design for general-purpose real-time processors. This document is divided into three parts of which the first is a summary of the material in the second and third sections. The second section discusses performance features of current processors that make them unsuitable for real-time computing and proposes alternative features to achieve high performance while supporting real-time needs. The third section discusses the merits of using intermediate level vision as the driving application for the design of a true real-time processor.

The RISC processor features that provide high performance are {\em probabilistic} (e.g., cache, TLB, writebuffers, branch prediction, etc.), so worst-case analysis in real-time systems must regularly assume the pathological conditions that make these features perform poorly (e.g., every cache access conflicts). This report presents analytical results of performance penalties due to worst-case execution time (WCET) estimates for RISC processors in real-time systems. The results clearly indicate where efforts should be made to reduce variability in processor designs.

In real-time computing the correctness of the system depends not only on the logical result of the computation, but also on the time at which the results are produced. Thus, much of real-time computing relies on predicting worst-case execution times (WCET). The increasing computational demands of today''s real-time systems require architecturally advanced processors be used. These advanced processors must have a TLB, cache memory, memory write buffer, out-of-order execution, branch prediction, deep pipelines, and multiple functional units. While these high performance architectural features enhance the average performance, they can add considerable variance to the WCET predictions of programs. The first section of this paper discusses how to incorporate advanced processor features while maintaining tight WCET predictions; the tradeoff is a slight loss in performance for lower variability. We show how a design for real-time can co-exist with a traditional design as a software mode that can be selected dynamically. The second section compares RISC processors and digital signal processors (DSPs) as to their real-time strengths and weaknesses and we estimate the design effort to correct their respective weaknesses. We conclude that current RISC processors match real-time processing needs much more closely than current DSPs.