The multiple-zone junction termination extension (MJTE) is a widely used SiC edge termination technique that reduces sensitivity to implantation dose variations. It is typically implemented in multiple lithography and implantation events. To reduce process complexity, cycle time, and cost, a single photolithography/implantation (P/I) MJTE technique was developed and diodes with 3-zone and 120-zone JTEs were fabricated on the same wafer. Here, the process tolerance of the single (P/I) MJTE technique is evaluated by performing CCD monitored blocking voltage measurements on diodes from the same wafer with the 3-zone and 120-zone single (P/I) JTE. The 3-zone JTE diodes exhibited catastrophic localized avalanches at the interface between the 2nd and 3rd zones due to abrupt zone transitions. Diodes with the smooth transitioning 120-zone JTE exhibited no CCD detectable avalanches in their JTE regions up to the testing limit of 12 kV. Under thick dielectric (deposited for on-wafer diode interconnection), diodes with the single P/I 3-zone JTE failed due to significant loss of high-voltage capability, while their 120-zone JTE diode counterparts were minimally affected. Overall, the single (P/I) 120-zone JTE provides a process-tolerant and robust single P/I edge termination at no additional fabrication labor.

Modern power conditioning systems require large active area devices which can support high currents. Though the breakdown and thermal properties of SiC make it an excellent choice for power switching applications, active area size is currently limited due to material and processing defects. One alternative is to parallel discrete diced die to achieve large active areas. However, this increases cost and complexity through dicing, soldering, and forming multiple wire bonds. Furthermore, paralleling discrete devices increases package volume/weight and reduces power density. To overcome these issues and achieve devices of high current switching capabilities, thyristors were designed and fabricated for the purpose of wafer-scale interconnection - which avoids the need of dicing and bonding and can achieve significant current density improvement over the paralleled diced device approach. Discrete thyristors fabricated for interconnection exhibited excellent yields and good uniformity of both blocking and on-state characteristics, showing great promise for large-scale interconnection.

To meet the large current handling requirements of modern power conditioning systems, paralleling of a large number of devices is required. This increases cost and complexity through dicing, soldering, and forming multiple wire bonds. Furthermore, paralleling discrete devices increases package volume/weight and reduces power density. To overcome these complexities, PiN diodes were designed, fabricated at high yields, tested, and interconnected on a three-inch 4H-SiC wafer to form an 11.72 cm 2 active area wafer-scale diode. The waferscale diode exhibited a breakdown voltage of 1790 V at an extremely low leakage current density of less than 0.002 mA/cm 2 . Under pulsed conditions, the peak current through the wafer-scale diode was 64.3 kA with a forward voltage drop of 10.3 V. The dissipated energy was 382 J and the calculated action exceeded 1.7 MA 2 -s. Preliminary development of high voltage interconnection has produced quarter wafer interconnected PiN diodes with active areas of 2.2 cm 2 and 3.1 cm 2 , exhibiting breakdown voltages of 4.5 kV and 4.0 kV, respectively.

The multi-zone junction termination extension (MJTE) is a widely used edge termination technique for achieving high voltage SiC devices. It is commonly implemented with multiple lithography and implantation events. In order to reduce process complexity, cycle time, and cost, a single photolithography and single implant MJTE technique has been successfully developed. The method utilizes a pattern of finely graduated oxide windows that filter the implant dose and create a graded MJTE in a single implant and single photolithography step. Based on this technique, 6 kV / 0.09 cm2 PiN diodes were fabricated utilizing a 120-zone single-implant JTE design. This novel single-implant MJTE design captures 93% of the ideal breakdown voltage and has comparable performance and yield to a baseline three implant process.

To meet the large current handling requirements of modern power conditioning systems, paralleling of a large number of devices is required. This increases cost and complexity through dicing, soldering, and forming multiple wire bonds. Furthermore, paralleling discrete devices increases package volume/weight and reduces power density. To overcome these complexities, PiN diodes were designed, fabricated at high yields, tested, and interconnected on a three-inch 4H-SiC wafer to form an 11.72 cm(2) wafer-scale diode. The wafer-scale diode exhibited a breakdown voltage of 1790 V at an extremely low leakage current density of less than 0.002 mA/cm(2). Under pulsed conditions, the peak current through the wafer-scale diode is 64.3 kA with a forward voltage drop of 10.3 V. The dissipated energy was 382 J and the action exceeded 1.7 MA(2)-sec.