AlGaN/GaN Super-Lattice Castellated Field Effect Transistors (SLCFETs) have been investigated under off-state gate and drain stress bias. Transfer and Capacitance-voltage (CV) characteristics are monitored during the measurement phase of a stress-measure-stress sequence and again after a three-day recovery period during which no bias is applied to the device. Three distinct peaks in the derivative of the CV curve (dCdV) are observed, illustrating that the SLCFET effectively operates as three devices in parallel: the top channel, the bottom channel, and the center channel transistor. A decrease in drain current (ID) and positive shift in the threshold voltage (Vth) was observed after significant stress, which was mostly recoverable. However, permanent shifts in the peaks of the dCdV curve are observed, with the largest shift corresponding to the top channel. These results suggest off-state degradation mainly occurs near the topside of the gate dielectric-AlGaN interface, leading to a channel dependent reliability behaviour.

We present the performance enhancement of GaN super-lattice castellated field-effect transistors (SLCFETs) following the integration of near-isotropic polycrystalline diamond (PCD) on top as a heat spreader. This integration has led to an approximately 14% increase in saturation current (up to similar to 2.63 A/mm) alongside a negative threshold voltage shift, while gate leakage and off-state current still have remained nearly constant. A tensile strain, which causes a negative threshold voltage shift by increasing the 2-dimensional electron gas density, was identified in the GaN channel. A significant reduction in temperature (from similar to 78 degrees C to similar to 47 degrees C at 6 W/mm) was observed after PCD integration, resulting in an increase in transconductance (from 652 mS/mm to 684 mS/mm). Also, comparable pulsed IV characteristics and small-signal gains were observed in devices with and without PCD.

Aluminium gallium nitride/gallium nitride (AlGaN/GaN)-based superlattice castellated field-effect transistors are a potential basis for high-power radiofrequency amplifiers and switches in future radars. The reliability of such devices, however, is not well understood. Here we report transistor latching in multichannel GaN transistors. At the latching condition, drain current sharply transits from an off-state value to a high on-state value with a slope less than 60 mV per decade. Current–voltage measurements, simulations and correlated electroluminescent emission at the latching condition indicate that triggering of fin-width-dependent localized impact ionization is responsible for the latching. This localization is attributed to the presence of fin-width variation due to variability in the fabrication process. The latching condition is reversible and non-degrading, and we show that it can lead to improvement in the transconductance characteristics of transistors, implying improved linearity and power in radiofrequency power amplifiers. A distribution in fin widths, due to variability in the fabrication process, can be used to study a latching condition in gallium nitride transistors in which drain current sharply transits from an off-state value to a high on-state value with a slope of less than 60 mV per decade.

Abstract AlGaN/GaN-based Superlattice Castellated Field Effect Transistors (SLCFET) are the foundation for high power RF amplifiers and switches for future radars, although their reliability is not yet well understood. Transistor latching is observed in GaN transistors for the first time. At the latching condition, drain current (ID) transits from an OFF-State value to high ON-State value sharply with a slope less than 60 mV/decade. Current-voltage (I-V), simulations and correlated electroluminescent (EL) emission at the latching condition indicates that triggering of fin width dependent localized impact ionization is responsible for latching. This localization is attributed to the presence of fin width variation arising due to variability in the fabrication process. The reversible and non-degrading nature of the latching condition is promising for next generation RF applications.

A electroluminescence (EL) based methodology has been devised to screen AlGaN/GaN Super-Lattice Castellated Field Effect Transistors (SLCFETs). EL intensity captured during off-state stressing has been correlated with an increase in gate leakage current after stress. Two off-state constant-voltage stress conditions were used, both applied over a stress time (t stress ) of 90 seconds: (a) V GS = -12 V, V DS = 12 V, and (b) V GS = -12 V, V DS = 14 V. The integrated EL intensity was found to scale with the ratio of off-state gate leakage current before and after the stress. The results were verified using step-stress tests to find the breakdown voltage (BV) of the gate dielectric of the stressed devices. BV was again found to scale with the measured integrated EL intensity for both the stress conditions. The results show that a short duration off-state stress in conjunction with EL can be a beneficial tool for quick assessment of the quality of gate dielectric across the wafer without incurring any significant damage to the devices. This becomes especially useful for rapid on-wafer device screening during large-scale production.

Accelerated OFF-State stressing of multichannel AlGaN/GaN Superlattice Castellated Field Effect Transistors (SLCFET) with varying dielectric thickness (di) and fin-width (Wfin) was studied using noise measurements. As di increased, the failure mechanism changed from an abrupt breakdown to gradual time dependent dielectric breakdown (TDDB). Smaller Wfin is found to extend lifetime compared to wider Wfin under such stressing condition. Percolation theory and associated trap generation during stressing can explain the observed behavior.

Hot electron effects have been studied in multichannel AlGaN/GaN-based Superlattice Castellated Field Effect Transistors (SLCFET). Current-Voltage (I-V) and simulations could identify channel position-dependent impact ionization within the device fins. Electroluminescence (EL) emission is observed simultaneously with the impact ionization, whose spectral analysis shows the signature of hot electron scattering (Bremsstrahlung radiation) and not electron-hole recombination.

We report on the development of the super-lattice castellated field effect transistor (SLCFET) technology as a candidate for the next generation of mmW and $W$ -band systems, leveraging the high carrier density and a high degree of charge control offered by this device topology for mmW and $W$ -band power amplification. The SLCFET is built using a superlattice of stacked AlGaN/gallium nitride (GaN) heterostructures that are etched into nanoribbons between epitaxial regrown n+ GaN source and drain contacts and controlled with a 100 nm length T-gate that electrostatically actuates the stacked channels from the sidewalls. The $2\times 20\,\,\mu \text{m}$ amplifier cells of SLCFET devices were measured using load–pull at 94 GHz using a 12-V bias, demonstrating amplifier output power densities of 10.87 W/mm with 43% power added efficiency (PAE) at peak power and a maximum linear gain of 5.4 dB. The SLCFET amplifier process attains this power density due to its extremely high current density, with an IMAX of 4.8 A/mm, along with its minimal dispersion, with current collapse measured using pulsed $I$ – $V$ at < 7%. The SLCFET technology, with its previously demonstrated world-class RF switch performance and now record $W$ -band amplifier performance, is ideal for use in next-generation mmW and $W$ -band systems.

Multichannel RF power amplifiers offer high frequency operation, high current and RF power, combined with excellent linearity. 3D and 2D simulation is used to investigate how changes in device architecture impact both the linearity and off-state reliability, allowing an improved linear design which does not compromise reliability. Linearity is assessed by extraction of g m 3 / g m ′ ′ , and third order intercept (TOI) as a function of gate bias, using a straightforward 2D approximation which is computation time and resource efficient compared to the full 3D simulation normally used for these devices. Off-state reliability is assumed to be linked to dielectric failure, and hence peak electric field as a measure of reliability is evaluated at gate corners and edges using a full 3D simulation. It is found that introducing a channel number-dependent doping in the AlGaN/GaN-based superlattice structure can be used to enable an improved transconductance–linearity. It is also found that there is a strong increase in TOI as gate dielectric thickness or fin width is increased. On the other hand, in order to maintain reliability, increased fin height is found to be essential in order to reduce electric field as dielectric thickness is increased. Finally, a device architecture for improving linearity, power and reduced OFF-state field is suggested.

Next generation RF systems require RF components capable of maintaining their performance across increasingly wide, multiple octave frequency bandwidths, supporting the operational flexibility and adaptability that is a primary feature of the direct signal conversion based digital back-ends of these architectures. The Superlattice Castellated Feld Effect Transistor (SLCFET) uses stacked AlGaN/GaN heterojunctions that have been etched into parallel nanoribbons between source and drain, in combination with a three dimensional gate structure providing control of the resulting transistor by simultaneously addressing the charge in each individual 2DEG layer of the stacked heterostructures through the sidewalls of the nanoribbons. The device structure of the SLCFET was specifically engineered as a solution to the limits of RF switch performance in FETs that inhibits wideband RF switch based circuit performance, due to the SLCFET topology’s inherent capability of decoupling the transistor’s ON resistance from its OFF capacitance [1] . Since this technology’s first appearance in publication [2] , the process has matured and been extended, with both 6-channel and 10 channel heterostructure based transistors and RF switch MMICs demonstrated [3] , and the 6-channel RF switch process having been qualified and productized, Fig. 1 [4] . The flexibility and broad capabilities of the SLCFET technology as both a high power switch and a low loss, high linearity, fast switching technology have subsequently been demonstrated using this production RF switch process. The high power handling and switching capability of the SLCFET was demonstrated, with a low loss and high isolation 0.1–4 GHz 100W SPDT switch [5] , while the fast switching, high linearity capabilities of the SLCFET were highlighted by the demonstration of a 0.4–2 GHz reconfigurable bandpass filter [6] . The 100W SPDT design demonstrated 10x greater isolation along with ~10% improvement in loss while requiring a ~37% smaller MMIC size than a GaN SPDT designed for the same frequency and power level built using a commercial conventional device process, Fig. 2 . The reconfigurable filter provides over 500 different filter channels, with variable bandwidth and center frequencies, Fig. 3 , all integrated into a single integrated circuit, providing an average of 2 dB improvement for each filter channel in NF and insertion loss, along with ~40x more power handling and ~20x greater linearity than an identical filter built using a state-of-the-art GaAs pHEMT process.

The super-lattice castellated field-effect transistor (SLCFET) is a multi-channel AlGaN/GaN HEMT device emerging as a technology platform for RF front ends, integrating world-class RF switches with high-performance RF amplifiers on the same wafer. This paper reports the performance results of a SLCFET amplifier device using an ALD TiN T-gate, which are improved with respect to previously reported data, with measured f t and f max up to 99 and 152 GHz respectively. The improvement is attributed to a reduced gate capacitance due to a higher T-gate hat without significant penalty of loss in gate control or increase of gate resistance. We also report W-band (94 GHz) large signal load-pull performance of the device with 4.33 W/active mm output power and 19.2% PAE. The process also demonstrates excellent DC/RF dispersion gate lag <1% and drain lag <2% and high breakdown voltage of 55 V.

We report a novel noise analysis for the leakage current during time-dependent dielectric degradation under bias stress, illustrated using AlGaN/GaN superlattice castellated field-effect transistors (SLCFETs). Gate step stress is a standard approach to test the robustness of the gate dielectric in OFF-state conditions. Here, by removing the background step transients measured using a standard parameter analyzer, the algorithm gives a quantitative value for the nonstationary superimposed noise in the dielectric leakage current during the test. Extraction of the power spectrum using windowing and a direct fit to the noise statistical distribution gives the noise magnitude. Although the technique allows the monitoring of noise increase during stress, it is shown that this is insufficient to clearly identify irreversible degradation in these devices. An additional low bias noise test between each step-stress bias has been used to detect the onset of permanent localized breakdown. This is manifested as both a change in noise magnitude and frequency dependence, occurring before it can be seen in leakage current or direct noise measurements.

This paper reports frequency performance improvements in Superlattice Castellated Field Effect Transistor (SLCFET) amplifier through device scaling. Device scaling incorporates the variations in castellation ridge width, castellation trench width, castellation length, gate stem length, gate hat length, gate offset, gate dielectric thickness, and passivation thickness. Highest ${f_{T}}$ and Fmax (70GHz/150GHz) values were achieved on devices with shortest castellation length. Shortening castellated access region reduces series resistance resulting in improved frequency performance. Thinner gate dielectric improves transconductance resulting enhancement in frequency performance as well.

This paper reports improvements in the Superlattice Castellated Field Effect Transistor (SLCFET) 10-channel device process to enable fabrication of ultra-wideband DC-110GHz Single Pole Double and Triple Throw (SPDT/SP3T) MMICs. The 10-channel SLCFET device offers higher performance, but is more difficult to fabricate. Through planarization of the device contact pads, the fabrication of the gate electrode is improved, thereby improving DC yield for the devices by more than 50%. Additionally, the planarization has enabled the scaling of the device source/drain spacing to 64% of baseline devices while maintaining a greater than 50% DC yield. The decrease in the source/drain spacing reduces on-resistance while minimally impacting the off-capacitance, leading to a higher achievable switch Figure of Merit Fco >3THz. The improved FET designs demonstrated improved insertion loss in the wideband SPDT and SP3T MMICs while showing no change in isolation. These ultra-wideband MMICs offer better insertion loss and bandwidth than is possible from other conventional technologies.

We report on the successful fabrication and demonstration of a low loss, high performance reconfigurable bandpass filter technology. A digitally reconfigurable bandpass filter was implemented by placing the low pass and high pass reconfigurable filters in series. Reconfigurable low pass and high pass filters were implemented by combining MMICs with RF switches selecting capacitor values and off chip high Q fixed inductors. The same circuitry was implemented in both a commercial GaAs pHEMT process as well as Northrop Grumman’s GaN based SLCFET technology. The resulting reconfigurable bandpass filter operates between 1.0-2.0 GHz, with over 500 different filters selections and supporting variable center frequencies as well as variable bandwidth sizes ranging from 70 MHz to 100 MHz, all in a single device. Depending on the center frequency and bandwidth of the selected path, the SLCFET based switched reconfigurable filters demonstrated a NF and insertion loss improvement over the GaAs variant by > 2 dB, while demonstrating an P1dBaverage of 33.6 dBm, compared to an average P1dBaverage= 17.8 dBm power handling of the GaAs reconfigurable filter. The SLCFET based filter was measured as having 20x greater linearity than the GaAs filter, with the average two tone IIP3 for the SLCFET filter at 43 dBm, compared to 30 dBm for the GaAs design.

Accurate compact model for simulating radio-frequency (RF) switch characteristics of a Super Lattice Castellated Field Effect Transistor (SLCFET) is presented. The new model is developed by modifying the industry standard ASM-HEMT compact model formulations. It is found that multiple channels of SLCFET cause unique I-V and S-parameters behavior of this technology. An accurate, and computationally efficient compact model is obtained after modifying ASM-HEMT formulations for multi-channel device electrostatics in SLCFET. The model is shown to be in good agreement with measurements for DC and RF device characteristics.

Efficient, high power density RF signal amplification is a driving enabler for future RF systems. The Super-Lattice Castellated Field Effect Transistor (SLCFET) leverages a GaN-based superlattice to support multiple stacked 2D-Electron Gas (2DEG) layers, thereby increasing its charge density compared to conventional GaN transistors by as much as 10x, directly boosting output power density. The low sheet resistance of the stacked 2DEG superlattice layers lowers device contact and source resistances, resulting in a low knee voltage. In addition, the SLCFET uses a three-dimensional, low resistance gate electrode to maintain healthy device electrostatics, high output resistance, and low input resistance. With these advantageous device characteristics, the SLCFET RF amplifier is able to provide record-setting output power density at mmW frequencies with excellent power-added-efficiency and linearity. Measured transistor values show excellent potential for both power and low noise amplification applications. With I DS >2.4A/mm, f T =50GHz, f max =100GHz, we are able to demonstrate Pout= 9.5W/mm, PAE = 41 %, and OIP3/P1dB =14dB at 30GHz.

The Super-Lattice Power Amplifier with Diamond Enhanced Superjunction (SPADES) device is being developed to enable a 2x increase in breakdown voltage of a Super-Lattice Castellated Field Effect Transistor (SLCFET) device. Incorporation of a diamond superjunction (SJ) within the drain region of a SLCFET was previously predicted to improve breakdown voltage with minimal impact on performance. P-type doped nanocrystalline diamond (NCD) is grown within etched trenches in the drain region of a SLCFET and tied to the gate, forming an active vertical field plate to laterally distribute electric field. Under high drain bias, mutual depletion regions are formed in the current carrying ridges and NCD in the drain region. This results in lower parasitic capacitance compared to a metal field plate, an important consideration for millimeter wave applications. On devices with an NCD SJ, we observe minimal capacitance penalty, low dispersion, and breakdown voltage behavior consistent with TCAD model prediction.

Heat extraction from novel GaN/AIGaN superlattice castellated field effect transistors developed as an RF switch is studied. The device thermal resistance was determined as 19.1 +/- 0.7 KAW/mm) from a combination of Raman thermography measurements, and gate resistance thermometry. Finite element simulations were used to predict the peak temperatures and show that the three-dimensional gate structure aids the extraction of heat generated in the channel. The calculated heat flux in the castellations shows that the gate metal provides a high thermal conductivity path, bypassing the lower thermal conductivity superlattice, reducing channel temperatures by as much as 23%.