LDMOS (laterally-diffused-metal-oxide-semiconductor) technology has been studied rigorously for high power and high voltage applications in communication systems, wireless networks, and high-frequency circuits, etc. due to its high voltage handling capability, high power density, low on-resistance, high linearity, etc. Often the device has to face radiation hazards for applications eg. space shuttles, drones, etc. Power transistors face hot carrier degradation (HCD) with total ionizing dose (TID) radiation and the overall performance of the device is degraded with radiation. Reducing or eliminating HCD from an LDMOS needs device structure modification which is often challenging and costly. There is a strong correlation between HCD and TID when coexist. It is important to study the LDMOS under radiation, especially for analog circuit performance parameters. In this work, the laterally defused LDMOS is extensively studied with a Sentaurus device simulator, for circuit application parameters such as threshold voltage (V-TH), transconductance (G(M)), cut-off frequency (f(T)), output resistance (R-0), and parasitic capacitances under total ionizing dose (TID) radiation. The device is also studied for low-frequency (1/f) noise under radiation. The simulation is well-calibrated with experimental results. As experimentally verified earlier, in this device TID can essentially upsurge the overall HCD-limited lifetime of an LDMOS transistor unexpectedly. In addition to better HCD behavior, the device offers better analog performance parameters and 1/f noise performances under TID radiation.

This work aims for an analytical model of surface potential and threshold voltage for a short channel Junctionless Cylindrical Gate All-Around (JL-CGAA) transistor. Surface potential has been derived from 2-D Poisson’s equation for cylindrical structure with some effective approximations and suitable boundary conditions considering both fixed charges and mobile charges of the device, using Evanescent method. The derived model is valid for all the regions of operations of the device, i.e., from subthreshold to accumulation region. Also, the effects of various physical device parameters such as oxide thickness, channel thickness on the surface potential are studied in this work. Both model and simulation results are in close agreement for different supply voltages.

Junctionless transistor (JLT) is known for improved short channel effects (SCE) and hence better scalability, and high temperature advantages, in addition that it offers more convenient fabrication steps. A Tunnel Field Effect Transistor (TFET) offers theoretically possible limit of subthreshold swing (SS) and has applicability for low power electronics. TFETs demonstrated in junctionless mode led to the evolution of JL-TFETs. This work analyses the performance of a JL-TFET for high temperature applications and the same is compared with a conventional p-i-n Silicon-on-Insulator Tunnel Field Effect Transistor (p-i-n SOI-TFET) at same threshold voltage. Using calibrated technology computer-aided design (TCAD) simulations, analog circuit performance parameters such as transconductance (Gm), gate-to-source capacitance (CGS), gate-to-drain capacitance (CGD), and cut-off frequency (fT) are analyzed for variation in temperature. Response to temperature is represented in terms of electrical parameters such as threshold voltage (VTH), on-off current ratio (ION/IOFF), subthreshold swing (SS). The ON-state current of the JL-TFET increases in order of hundreds of μA/μm at high temperature, whereas p-i-n SOI-TFET shows lesser temperature sensitivity.

Junctionless transistor (JLT) which does not have a PN junction in the source-channel-drain path, is reported to have a lower OFF-state current and therefore is more scalable to lower channel lengths compared to a conventional MOSFET, moreover a JLT also offers easy fabrication steps. Tunnel FET (TFET) provides a theoretically possible limit of subthreshold swing (SS) and has applicability for low-power electronics. Combining junctionless technology in a TFET (JL-TFET), the possible application of the device is looked into, for further low-power and high-temperature applications. This work analyses the performances of a JL-TFET for high-temperature applications and the same is compared with a conventional p-i-n silicon-on-insulator tunnel field effect transistor (p-i-n SOI-TFET). Using calibrated technology computer-aided design (TCAD) simulations, analog circuit performance parameters like ON-state to OFF-state current ratio ( I_ON/I_OFF ), subthreshold slope (SS), transconductance ( G_m ), gate-to-source capacitance ( C_GS ), gate-to-drain capacitance ( C_GD ), and cut-off frequency ( f_T ) etc. are analyzed for temperatures till 500 K. ON-state current of JL-TFET increases in the order of hundreds of μA/μm at high temperatures, whereas p-i-n SOI-TFET shows lesser temperature sensitivity. JL-FET is more applicable to low-power applications, whereas a p-i-n SOI-TFET has more suitability for high-speed applications. Dual material technology adoption helps in improving the ambipolar behavior of the device. Analysis of interface traps is carried out in this architecture where the concentration, energy positions, and energy width of the distribution of acceptor-like and donor-like traps at the interface of semiconductor and oxide are also evaluated.

Junctionless FETs exhibit better high-temperature performance than their traditional inversion-mode (IM) counterparts due to reduced scattering in the substrate-oxide interfaces. In this work, a double-gate junctionless SiC FET with an embedded P+ pocket in the oxide layer (P+-SiCJLT) is studied for DC and AC performance for high-temperature and high-voltage applications using calibrated TCAD simulations. The advantages of P+-SiCJLT are manifold: (a) it offers efficient volume depletion and therefore can be scaled to lower channel lengths, (b) it improves the ON-state to OFF-state current ratio, (c) it improves the intrinsic gain, and (d) it promotes enhancement-mode operation in traditional depletion-mode FETs. These advantages become apparent when the P+-SiCJLT is compared with a device of similar dimensions without the P+ layer (SiCJLT). Moreover, P+-SiCJLT offers better electrostatics and $${{I}}_{{ON}}/{{I}}_{{OFF}}$$ ratio than a SiCJLT with P+ pockets near the source/drain regions (SDPocket-SiCJLT).