We developed a 32 kB embedded nonvolatile memory (NVM) intellectual property (IP) using 2T-SONOS cells. Although SONOS cells possess intrinsic defect immunity, we discovered abnormal memory cell failure during the probe test of the IP. The major failed items are checkerboard (CKBD), inverse CKBD, and gate-with-source (G-S) disturbance at the erased state. The threshold voltage distributions and electrical failure analysis (FA) reveal that all major failures occurred because of an abnormally weak G-S disturbance immunity. In addition, the temperature dependency of the G-S disturbance implies that the failure mechanism is related to Co-spike rather than midgap trap-induced junction leakage. Although abnormal defects are not detected through physical FA, by using simple failure modeling and a process split test, we verified the root cause of a new type of erratic failure. The single-bit disturbance failure can be explained as electrons generated in the floating junction area being accelerated in the G-S stress mode, resulting in soft programming by the channel hot electron (CHE) injection mechanism.

We have analyzed the program disturbance immunity mechanism of a vertical assist-select gate lateral coupling (VA-SGLC) cell. Comparing different operation methods of unit cells fabricated with the same process, we verified the array structure and operation mode dependence of the program disturbance. As an embedded nonvolatile memory, the VA-SGLC cell offers advantages of no additional masks and process steps as well as fast program speed and program/erase cycling performance exceeding 10 k. Furthermore, it exhibited abnormally strong disturbance immunity. Using worst-case disturbance measurements and potential difference comparisons, we verified the mechanism of the abnormally strong disturbance immunity of the VA-SGLC cell. The strong program disturbance immunity of VA-SGLC cell is due to the varying coupling ratio caused by coupling dividing operation methods. These features arise from the distinctive array structures and operation methods of the VA-SGLC cell.

Second harmonic generation (SHG) characteristics of single and multilayer field-effect passivation (FEP) structures were investigated for CMOS image sensor application. By compensating the internal multiple reflection effect, the SHG characteristics of single and multilayer FEP structures were compared under equivalent conditions. Analysis of the time-dependent SHG intensity confirmed that the multilayer FEP structure has a 2.7 times higher SHG intensity than the single-layer structure, and the FEP layer is negatively charged from the initial state. In particular, when atomic layer deposition conditions were varied to control the Al2O3 composition ratio, the SHG demonstrated greater detecting sensitivity than conventional material analysis methods such as RBS and XPS, even though it cannot distinguish the elements. Moreover, SIMS composition analysis verified that the initial state SHG intensity increase under high oxygen ambient Al2O3 growth condition can be attributed to the change of impurities rather than the effect of oxygen areal density increase.

We report a low-cost and highly reliable 2T-SONOS embedded nonvolatile memory (eNVM) using a novel contamination-free process integration. The proposed 2T-SONOS cell is fabricated on a 90-nm high-voltage CMOS process for a touch screen controller embedded display driver IC applications. For a code storage purpose, eNVM with moderate memory density, simple integration, platform logic and process compatibility, and sufficient retention lifetime are critically important. Thanks to the contamination-free charge trap layer and optimized junction, we have achieved enough retention lifetime without using any special materials for the charge trap layer. The 120 degrees C data retention lifetime of over 10 years is verified using 77 samples of 32-kB memory density intellectual property. By correlating high-temperature retention bake results with technology computer-aided design simulations, we can understand long-term charge redistribution behavior inside trap nitride, which is significantly different from floating gate type NVM.

In this paper, we have evaluated select gate lateral coupling (SGLC) cell by using a 4kbits (kb) macro. Using large data cell VT distributions, tail bit behavior can be analyzed. The test chip is fabricated on a 90 nm high voltage CMOS process without any additional steps. Thanks to the unique lateral coupling operation method, the size of the SGLC cell is comparable to SRAM of the same technology node resulting in the smallest single-poly non-volatile memory (NVM) cell size of 1.34 μm2 at 90 nm technology node. However, because of the high aspect ratio of unit cell geometry of 3.28 : 1, it was difficult to arrange word-line and bit-line decoder efficiently. For the 4-kb SGLC cell macro, by structuring the top and bottom side located cell addressing decoders, we achieved efficient decoder architecture and further memory density extension capability. Through the 150 ºC retention bake test, we analyzed the possible retention weak cells that may be generated by the silicide-FG structure. As a result, over 10-years lifetime for code storage applications is verified without tail bit occurrences.

We report on a low cost, secure 2T-SONOS embedded nonvolatile memory (eNVM) using a novel contamination free process integration. The proposed 2T-SONOS cell utilizes reverse read method resulting in wide threshold voltage ( $\boldsymbol{V_{T}}$ ) window read margin. Using an eNVM on a 90 nm high voltage CMOS process, touch screen controller (TSC) embedded display driver IC application as well as wide input range TSC is possible. Unit cell shows 6 volt program and erase $\boldsymbol{V_{T}}$ window. However, 32 kB IP shows lower $\boldsymbol{V_{T}}$ window of 2 V due to cell $\boldsymbol{V_{T}}$ distribution, source side resistance and program disturb effect during programming. In case of programmed cells, both fresh and 1 k program/erase (P/E) cycled cells show abrupt initial $\boldsymbol{V_{T}}$ shift of 0.5 V after 48 hours of 120 °C bake test. However, erase $\boldsymbol{V_{T}}$ shift happened only at 1 k P/E cycled cell. Regardless of cycling and program/erase states, after 48 hours of bake, $\boldsymbol{V_{T}}$ shift was saturated. Thanks to the charge trap layer contamination suppressing novel process integration and optimized charge distribution, 120 °C data retention lifetime of over 10 years after 1k P/E cycling is obtained without using any special band gap engineered materials.

Second harmonic generation (SHG) characteristics of single and multilayer field effect passivation (FEP) structure were investigated for CMOS image sensor application. By compensating the internal multiple reflection (IMR) effect on SHG intensity, the characteristics of single and multilayer FEP structures were compared under equivalent conditions. FiniteDifference Time-Domain simulation reveals that due to IMR effect, the intensity of multilayer structure was reduced to around 60 % than the single FEP layer regardless to thin film thickness and refractive index variation. The major IMR effect difference was caused from 390 nm outgoing SHG signal. Analysis of the timedependent SHG intensity confirmed that the multilayer structure has a 2.7 times higher SHG intensity than the single layer structure. Also, the FEP layer is negatively charged from the initial state. In addition, when atomic layer deposition conditions were changed to control the Al2O3 composition ratio, the oxygen-rich growth condition shows higher SHG intensity than using oxygen deficient growth conditions.

This paper reports the process integration and fabrication characteristics of a vertical thin poly-Si channel (VTPC) transfer gate (TG) pixel, which is one of the candidates for future 3-D CMOS image sensor (CIS) applications. The proposed process integration can effectively suppress grain boundary formation at the interface between the photodiode and the poly-Si channel by solid phase epitaxial growth (SPEG) mechanism. Furthermore, dopant diffusion characteristics for source-drain junction formation in poly-Si substrates are investigated using secondary ion mass spectroscopy (SIMS) depth profiles under various process conditions. In addition, combining SIMS results with I-d-V-g curve and scanning spreading resistance microscopy measurements, we explained the discrepancy in diffusion characteristics between the bulk and the thin-film poly-Si. Finally, by using optimized SPEG conditions and adopting the proposed VTPC-TG pixel structures in a commercial 5-Mpixel CIS image sensor product, we successfully verified the improvement in image quality.

This paper reports the epitaxial-Si growth and dopant diffusion characteristics during fabrication of a vertical thin poly-Si channel (VTPC) transfer gate (TG) structured pixel, which is a possible candidate for future three-dimensional (3D) CMOS image sensor (CIS). Due to the increasing demand for higher resolution sensor, major CIS companies have presented various innovative 3D pixel structures of their own design. Recently, by adopting a structural concept similar to that of 3D NAND flash memories, a VTPC-TG structured pixel has been reported. However, grain boundary control and dopant diffusion behaviors in poly-Si have not been identified. The proposed process integration can suppress the dark current caused by grains of poly-Si in the VTPC-TG structured pixel by low temperature solid phase epitaxial growth. In addition, the channel punch-through caused by fast dopant diffusion in poly-Si can be suppressed by a thin poly-Si channel structure and process optimization.

The influence of electron and hole (EH) distribution on two-transistor (2T) silicon-oxidenitride-oxide-silicon (SONOS) embedded nonvolatile memory (eNVM) is investigated in terms of reliability. As PE (program/erase) cycles are repeated, it is observed that the electron distribution in the nitride layer becomes wider. It leads to the EH distribution mismatch, which degrades the reliability of 2T SONOS eNVM.

In this letter, we report a high-performance logic nonvolatile memory for pure logic processes using novel structure and operations. Even though a select gate lateral coupling (SGLC) cell has the advantages of small cell size, fast programming speed, and over-erase-free features, it has a critical problem of on-cell current degradation during a relatively small number of program/erase (P/E) cycles. By installing an assist gate (AG) on an SGLC cell and employing novel operation methods, the cycling performance improved significantly from 100 times to 10 k times. The initial purpose of using AG was for Fowler-Nordheim erasing operation. However, it is not only used for erasing operation but also for programming to enhance the coupling ratio using the novel vertical assist (VA) operating method. Owing to the novel VA-SGLC cell structure and combined vertical and lateral coupling operations, it shows enhanced programming speed, wider V T window, and higher endurance than the conventional SGLC cell using the same process. As a result, a program time of 10 μs and 10 k times P/E cycling performance, preserving a VT window of over 4 V, is achieved without additional processes or increasing the cell size.

In this letter, the image characteristics of CMOS image sensor (CIS) pixels using a vertical thin poly-Si channel (VTPC) transfer gate (TG) are established for the first time. The study of three-dimensional (3D) structures in the image sensor field has been started by 3D Flash memories. By adopting the poly-Si channel fabrication concept of 3D NAND flash memories—appropriately modified to fit the requirements of a TG in CIS pixel applications—the VTPC structure effectively suppresses the grain boundary effect. The VTPC-TG performance improves as the poly-Si channel becomes thinner. The possibility of implementing 3D pixel-based CIS is confirmed by applying the fabricated VTPC-TG to a mass-produced 1.12- $\mu \text{m}$ BSI product, and using it to capture 5-Mpixel images.

This paper clarifies the reason for the specific array structure and operation methods of a select gate lateral coupling (SGLC) cell array as well as its disturbance immunity. An SGLC cell is a type of single-poly embedded nonvolatile memory that does not require any additional masks and process steps for fabrication. It shows excellent features, such as high programming speed, small cell size comparable to that of SRAM, multitime programmable, and over-erase free characteristic. However, the reasons of its operation methods and cycling limitation have not yet been clarified. We investigated the cycling effect of two types of array structures based on the unit-cell operation method. In particular, in the forward read mode, because of drain-induced barrier lowering (DIBL) that is enhanced by trapped holes at the liner nitride, V T of a programmed cell significantly decreased with a relatively small number of program/erase (P/E) cycles, resulting in a narrower V T window. By adopting the reverse read mode with source-side programming, DIBL enhancement was suppressed and a stable V T window was maintained during P/E cycling. Furthermore, by measuring each disturb method that works with the SGLC cell array structure and the reverse read operation mode, we confirmed that an array size larger than 128-kB sectors is possible.

In this paper, we describe a new single poly MTP (multiple time programmable) cell using contact plate and select gate coupling manufactured by 90 nm standard CMOS (complementary metal-oxide semiconductor) process. Proposed MTP cell size is smaller than conventional well coupled MTP cell and only select gate lateral coupling MTP cell in order to have the similar coupling ratio (CR) as the 1.98~3.26 μm2. The program erase operation use channel hot electron injection (CHEI) and band to band hot hole injection (BTBT-HHI). The cell performances are compared with splits group by coupling ratio (CR). Through the results represented by the experiments, we were able to achieve cell endurance of 100 cycle and 10 year retention lifetime at 150 °C, and realize operation margin with ease if coupling ratio is increased by adding plate contact. The describing cell using coupling of select gate and plate contact is thought to have more useful application due to technology shrink.

In this letter, we propose a control-plug (CP) structure logic nonvolatile memory (LNVM) fabricated by a standard logic CMOS process for mobile applications with low-power-consumption requirement. The operating concept of this cell is based on the use of a lateral capacitance coupling between a bar-type CP and a floating gate. Owing to the unique bar-type CP-coupling method and CP-sharing cell array structure, the novel cell has a coupling ratio of over 94% with the lowest fill factor of 344 as a Fowler-Nordheim (FN)-operated LNVM. Furthermore, because of the high coupling ratio and divided-bias operating method, this cell utilizes a uniform-channel FN tunneling program and erase method using a 3.3 V logic peripheral overdrive tolerable voltage of 5.5 V.

We report a single-poly embedded nonvolatile memory (eNVM) solution for analog trimming and code storage applications using a 0.13-μm BCDMOS process. Each cell has its own merits and demerits, depending on structure and operation methods. For analog trimming purposes, a conventional n-well coupling Fowler-Nordheim tunneling cell with a large unit cell size of 88 μm2 is used. On the other hand, a select gate lateral coupling (SGLC) cell for code storage purposes has a much smaller unit cell size of 2.82 μm2, which is comparable to the size of SRAM. The SGLC cell is fabricated using a combination of only 1.5-V and 5-V transistor-related processes for channel hot electron injection programming. The SGLC cell exhibits a high programming speed of 100 μs and is over-erase-free, which is suitable for a NOR array structure. In addition, both cells also had a retention lifetime of more than 10 years. Thus, these cells can be fabricated to match the requirements of various eNVM applications.

In this paper, the program and erase characteristics of a two-transistor (2T) SONOS nonvolatile memory (NVM) cell have been described by using one-shot simulations and device simulations. In addition, a mismatched charge distribution between electrons and holes has been verified through measurements and device simulations. The program and erase (P/E) operations are performed through channel hot electron injection (CHEI) and band to band tunneling induced hot hole injection (BTBT-HHI), respectively. Because a complete erase operation can't be achieved with longer control gate (CG) lengths, the optimized CG length is a key factor in the 2T SONOS device. The proposed cell uses the whole channel to achieve good reliability during the program and erase operations. Nevertheless, it is strongly suspected that excess electrons might gradually build up in the nitride layer toward the source junction because of spatial mismatches of the injected electrons and holes during P/E cycles. This phenomenon of electron build-up has been confirmed through both device simulations and real measurements of the gate length dependence of the program and erase speeds. As a result of gradual accumulation of electrons, the cell transconductance (Gm) continues to become reduced. The degraded Gm value is also observed to be noticeably improved after a process of bake retention.

We present a novel select gate (SG) lateral coupling embedded nonvolatile memory without any additional steps on a 90-nm high-voltage CMOS process. Usually, the SG coupling devices use a complex double poly process. However, continuing technology shrinkage makes the lateral coupling method possible for a single poly process. The SG of the novel cell is designed to function as a control gate and an SG at the same time, using only lateral capacitance coupling. Because of this distinct cell structure and operating principle, the memory cell has relatively small cell size, over-erase free, and multitime programmable features. The proposed cell is programmed by channel hot electron method and erased by band-to-band tunneling-assisted hot hole method, resulting in a 20-mu s programming time and 100-ms erasing time. In addition, using this condition, we can achieve over 3 V threshold voltage (V-T) window over 500 cycles and an estimated over 10 year retention lifetime at 85 degrees.