We compensate jitter between any two unsynchronized endpoints by tracking their clocks and re-creating flows by retiming packets. After implementation over FPGA, we achieve ~10ms synchronization setup time with no more than 70ns jitter.

This study investigates a new side-channel leakage observed in the inner rounds of an unrolled hardware implementation of block ciphers in a chosen-input attack scenario. The side-channel leakage occurs in the first round and it can be observed in the later inner rounds because it arises from path activation bias caused by the difference between two consecutive inputs. Therefore, a new attack that exploits the leakage is possible even for unrolled implementations equipped with countermeasures (masking and/or deglitchers that separate the circuit in terms of glitch propagation) in the round involving the leakage. We validate the existence of such a unique side-channel leakage through a set of experiments with a fully unrolled PRINCE cipher hardware, implemented on a field-programmable gate array (FPGA). In addition, we verify the validity and evaluate the hardware cost of a countermeasure for the unrolled implementation, namely the Threshold Implementation (TI) countermeasure.

Embedded technologies such as IoTs, connected cars or medical equipment are often executed in constrained environment with limited resources. The high demand of security makes cryptography essential. Moreover, the security must consider physical attacks as these objects are physically accessible and can be tampered with. Lightweight Cryptography (LWC) proposes interesting candidates for securing t...

Lightweight Cryptography (LWC) is suitable for IoTs which require a high level of security while keeping a low complexity. Many lightweight cryptographic algorithms have been proposed to satisfy these requirements. But there is currently no emerging standard concerning the symmetric block ciphering, as every algorithm has its own advantage. For instance one can be optimized for low latency, another one for low complexity but requires more rounds to be cryptographically secure to the detriment of throughput. Hence, a processor able to cope with all the algorithms should be ideal to provide agility, performance and security while keeping an affordable complexity. We present in this paper a specific execution unit of the RISC-V processor which is able to run the most common lightweight 64-bit block ciphers. The gain in performance can reach over a hundred compared to the reference architecture. The acceleration takes advantage of five specific instructions which can easily be adapted to the execution unit of a VexRiscv architecture. The complexity can double when implementing the new execution unit, but provide a high degree of agility and performance when executing most of lightweight cryptographic implementations.

Lightweight cryptography is at the heart of today’s security needs for embedded systems. The standardised cryptographic algorithms, such as the Advanced Encryption Standard (AES), hardly fits the resource restrictions of those small and pervasive devices. From this observation a plethora of Lightweight Block Ciphers have been proposed. Every algorithm has its own advantages in terms of security, complexity, latency, performances. This paper presents first a classification of some popular Substitution-Permutation-Networks (SPN) class of lightweight ciphers according to their architecture and features which share many common operators. From this last point, we studied a round-based generic hardware architecture that allows a security architect to dynamically change the lightweight cryptographic algorithms to be executed. The results of the ASIC implementation show that the configuration part of the proposed flexible architecture adds significant complexity. If compared with the parallel implementation of several algorithms, the complexity ratio becomes interesting when the number of algorithms (or the level of agility) increases. For instance, if we consider 6 SPN ciphers, the configurable architecture provides a complexity reduction of 62.5%, whereas there is no reduction with 4 algorithms.

Cryptography is a key element to the development of secure communication in embedded environments such as connected cars and IoT. For some specific applications specific Lightweight Block Ciphers (LBC) have emerged. Those algorithms have been designed to be less resource consuming and more flexible than standard cryptographic algorithms. In order to keep a high levels of performance for software implementation of those LBC, we propose to enhance the instruction set of microprocessors by adding custom instructions. This would allow the system designer to find the best compromise between flexibility requirements and efficiency in terms of throughput and latency. This paper first presents a classification of LBC according to their specific operations. Then, based on the open RISC-V ISA, we propose a set of custom instructions to enhance LBC execution. The comparison of both execution time and throughput between different levels of processor customization is presented. Our results showed a significant gain as the execution time can be reduced by a factor between 20 and 100 for some classes of LBC.

This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts.

An SR-latch can be regarded as primitive to build a True Random Number Generation (TRNG) or Physically Unclonable Function (PUF). Indeed, when the SR inputs of the latch are tied together and go from an unknown state (i.e. S=R=1) to a memory state (i.e. S=R=0), the behaviour depends on the balance between the NAND or NOR gates composing the latch. With the process mismatch, there is a great chance that the latch converges towards the same state, thus creating a PUF equivalent to a SRAM-PUF or latch-PUF. However, if the latch is well-balanced, it can enter a metastable state and converges to a stable state depending on the input noise, thus making a TRNG. In order to make sure some latches are able to behave like a TRNG, and some like a PUF, we consider a set of latches driven by the same SR signal. A test-chip in 28nm UTBB-FDSOI technology has been designed with 1024 latches in order to analyze the behavior. The FD-SOI technology enables easy change of the performances of gates using the body biasing, which consists in applying a specific body voltage to each gate. Hence, the two NOR gates composing the SR-latch can be tuned individually to get the optimality, i.e. the maximum entropy, for both PUF and TRNG. The results show that the optimal point is the same for both PUF and TRNG, and that the proposed structure can generate concurrently a PUF with high reliability, and a TRNG with high speed.

Fault injection attack is an extremely powerful technique to extract secrets from an embedded system. Since their introduction, a large number of countermeasures have been proposed. Unfortunately, they suffer from two major drawbacks: a very high cost on system performance and a security frequently questioned. The first point can be explained by their design, based on techniques from reliability domain, which result in solutions protecting against fault models either highly improbable in a context of attack, or that do not permit secret extraction. At the opposite, the second point is due to the use of an incomplete attacker model for the security evaluation at design step. In this paper, we propose a new approach: multi-level formal verification, based on models encompassing the capabilities of the attacker, the susceptibility to faults of the hardware platform hosting the implementation, and the constraints imposed by the algorithm used for secret extraction. We first explain that the success of a fault injection attack depends solely on races between signals, which can be analyzed automatically. Then, we perform a multi-level evaluation on a hardware implementation of AES-128, which shows that the overhead of a countermeasure can be divided by eight while maintaining an almost identical level of security. Finally, we extend the model to electromagnetic injection.

An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.

Fault injection attack is an extremely pow-\nerful technique to extract secrets from an embedded\nsystem. Since their introduction, a large number of\ncountermeasures have been proposed. Unfortunately,\nthey suffer from two major drawbacks: a very high cost\non system performance, and a security frequently ques-\ntioned. The first point can be explained by their design,\nbased on techniques from Reliability domain, which re-\nsult in solutions protecting against fault models either\nhighly improbable in a context of attack, or that do\nnot permit secret extraction. At the opposite, the sec-\nond point is due to the use of an incomplete attacker\nmodel for the security evaluation at design step. In this\npaper, we propose a new approach: multi-level formal\nverification, based on models encompassing the capabil-\nities of the attacker, the susceptibility to faults of the\nhardware platform hosting the implementation, and the\nconstraints imposed by the algorithm used for secret\nextraction. We first explain that the success of a fault\ninjection attack depends solely on races between signals,\nwhich can be analyzed automatically. Then, we perform\na multi-level evaluation on a hardware implementation\nof AES-128, which shows that the overhead of a coun-\ntermeasure can be divided by eight while maintaining\nan almost identical level of security. Finally, we extend\nthe model to electromagnetic injection.

Probing attacks are serious threats on integrated circuits. Security products often include a protective layer called shield that acts like a digital fence. In this article, we demonstrate a new shield structure that is cryptographically secure. This shield is based on the lightweight block cipher and independent mesh lines to ensure the security against probing attacks of the hardware located behind the shield. Such structure can be proven secure against state-of-the-art invasive attacks. Then, we evaluate the impact of active shield on the performance of security IPs as PUF, TRNG, secure clock and AES using a set of fabricated ASICs with 65 nm CMOS technology of STMicroelectronics. Also, the impact of active shield on Side-Channel Attack (SCA) is evaluated.

This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not require the adaptive digital synthesis filters. The timing mismatch is estimated based on an adaptive stochastic gradient descent technique, which is a promising solution for TIADCs operating at a very fast sampling rate. The digital circuit of the proposed calibration algorithm is designed and synthesized using a 28-nm fully depleted Silicon on insulator (FD-SOI) CMOS technology for the 11-b 60-dB SNR TIADC clocked at 2.7 GHz with the input in the first four NBs. The designed circuit occupies the area of 0.05 mm 2 and dissipates the total power of 41 mW.

In this paper we present quaternary and ternary routing tracks for FPGAs, and their implementation in 28nm FDSOI technology. We discuss the transistor level design of multi-valued repeaters, multiplexers and translators, and specific features of FDSOI technology which make it possible. Next we compare the multi-valued routing architectures with equivalent single driver two-valued routing architectures. We show that for long tracks, it is possible to achieve upto 3x reduction in dynamic switching energy, upto 2x reduction in routing wire area and 10% reduction in area dedicated to routing resources. The multi-valued tracks are slightly more susceptible to process variation. We present a layout method for multivalued standard cells and determine the layout overhead.We conclude with various usage scenarios of these tracks.

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

This paper presents a practical implementation of all digital calibration algorithm for the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converter (TI-ADC). A new Least Mean Square (LMS) based detection scheme is proposed to increase convergence speed as well as to enhance the estimate accuracy. Monte Carlo simulations for a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz show that SFDR can achieve approximately 90 dB SFDR within the stable point of the channel mismatch coefficients over the first three Nyquist Bands. The proposed architecture is implemented and validated on the Altera FPGA DE4 board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip and work properly on a Hardware-In-the-Loop emulation framework.