The performance and functionality of large language model (LLM)-based applications heavily depend on their contextual inputs. As applications become more sophisticated, their contexts grow increasingly complex, leading to two critical challenges: (i) excessive computational and memory overhead—particularly from the key-value (KV) cache—and (ii) heightened security risks arising from heterogeneous and unverified context sources. Existing approaches fail to address both issues simultaneously: context compression methods often discard crucial information, undermining instruction fidelity, while security-oriented defenses typically introduce additional computational costs. We present LevelKV, a hierarchical KV cache pruning framework that achieves efficient and reliable LLM inference. LevelKV employs a holistic metric to jointly identify critical activations in both Key and Value caches, and introduces a hierarchy-preserving mechanism that structurally prioritizes high-privilege prompts during pruning to maintain reliability. Evaluations on LongBench and SysBench demonstrate that LevelKV achieves state-of-the-art trade-offs between memory efficiency and instruction compliance. Remarkably, it maintains superior Instruction Hierarchy reliability even when retaining only 1/10 of the KV cache, enabling robust and efficient LLM deployment on memory-constrained devices.
Generative large language models (LLMs) face significant challenges in deployment due to their substantial computational and memory demands, particularly under batched inference scenarios. While activation sparsity offers a promising direction to reduce resource consumption, its benefits diminish with increasing batch sizes. Moreover, existing sparse inference systems fail to fully utilize modern GPU Tensor Cores. This paper proposes SpBatch, an efficient execution framework for batched activation-sparse FFN computation in ReLU-adapted LLMs through a two-level design. At the system level, it introduces Sparsity-Aware-Division to dynamically partition large batches into smaller mini-batches, maximizing sparsity and hardware utilization simultaneously. At the kernel level, it employs a “Load by CUDA Cores, Compute by Tensor Cores” strategy, alongside a Bitmap-based Neuron Index mechanism for load balancing and an optimized execution pipeline. SpBatch achieves up to 8.89× speedup over PowerInfer (a representative activation-sparse baseline) and up to 2.6× over llama.cpp (a dense inference framework) in end-to-end inference under the evaluated settings. These results demonstrate that activation sparsity and batch processing can be jointly leveraged through a selective sparse FFN execution path, especially in small-to-moderate batch regimes and high-sparsity edge-oriented scenarios where dense execution does not yet fully dominate.
Integration of Silicon-Photonic (SiPh) interconnects with multi-chiplet systems offers unprecedented bandwidth and energy efficiency for next-generation computing. However, the resulting high power density and complex vertical thermal coupling create severe thermal challenges that threaten both computational integrity and photonic communication reliability. Accurate and efficient full-chip thermal monitoring is a critical prerequisite for dynamic thermal management, yet it remains challenging. The limited number of physical thermal sensors that are often sparsely placed on the compute chiplets fails to capture the intricate 3D thermal landscape, especially within the photonic interposer network (PIN) itself. To this end, we propose TherMoPIN, a novel framework achieving accurate yet cost-effective full-chip thermal monitoring. In addition to the physical thermal sensors that are readily placed on chiplets, it repurposes the existing PIN into a uniformly placed virtual thermal sensor array with negligible cost increases. TherMoPIN comprises two key enablers. First, we propose ArbLink, a precise and cost-efficient thermal sensing mechanism, which transforms the entire PIN into a dense and uniformly-distributed ‘virtual’ sensor array by reusing available photonic routers for thermal sensing, with minimal hardware overhead. Second, we develop HorVer, a lightweight thermal reconstruction technique that fuses sparse, direct readings from horizontal on-chiplet thermal sensors (i.e., physical ones) with the dense, indirect thermal data from the vertical photonic interposer network (i.e., virtual ones), capturing and modeling the critical thermal coupling between the compute chiplets and the photonic interposer. This unique horizontal-vertical data fusion allows HorVer to accurately reconstruct the full-chip thermal map of SiPh-chiplet systems. Experimental results demonstrate that TherMoPIN achieves high thermal monitoring accuracy, significantly outperforming state-of-the-art (SOTA) methods that rely solely on physical sensors. Furthermore, it accomplishes this with negligible additional hardware cost, as it primarily reuses the already-present photonic infrastructure for sensing.
With the rapid expansion of data center networks and the growing complexity of network topologies, network failures have become inevitable, rendering reliability evaluation critical for the stable operation of data center networks. However, the unique non-regular clique-based structure of the high-performance server-centric ECQDC network makes traditional reliability assessment and fault diagnosis methods inapplicable, and its h-component reliability and fault identification problems have not been studied yet. To tackle this issue, this paper proposes a Component-Based Fault Diagnosis Model (CFM) to evaluate the reliability of the ECQDC network. Firstly, we derive the exact expressions of h-component connectivity for ECQDC, which serves as the structural foundation of the proposed model. Secondly, we determine the h-component diagnosability of ECQDC based on the CFM, extending the relevant theory to non-regular network topologies. Thirdly, we develop the H-CDA algorithm to achieve efficient fault identification for large-scale ECQDC networks. Experimental results demonstrate that the CFM delivers excellent structural resilience, and the H-CDA algorithm achieves a diagnosis success rate of 99.1% under random fault scenarios while retaining 94.8% under correlated cluster faults, with an F1-score above 0.96 across all tested failure patterns. These achievements provide a solid theoretical and practical basis for the reliability optimization of the ECQDC network.
Sparse Matrix-Vector Multiplication (SpMV) is a fundamental sparse kernel in both scientific computing and artificial intelligence. However, the performance of existing SpMV algorithms is highly sensitive to diverse sparsity patterns, necessitating an adaptive framework that can effectively extract matrix structures and predict optimal configurations. In this work, we first analyze the performance of parallel SpMV algorithms in various formats. Based on the analysis, we propose Sparsity-aware SpMV (SSpMV), a framework that integrates handcrafted expert features with multimodal representations to automatically determine the optimal algorithm and parameters. At its core is MM-Adapter, a novel multimodal convolutional neural network designed for this selection task. The robustness of SSpMV is validated using a diverse dataset, consisting of nearly the entire SuiteSparse Collection supplemented by finite element matrices. On an Intel Xeon 5120 CPU, SSpMV achieves a selection accuracy of 81.05% and a geometric speedup of 1.26× over the MKL spblas IE. Furthermore, on an NVIDIA A100 GPU, it yields 74.12% accuracy and a 1.31× speedup over the cuSPARSE baseline.
We present LearnedFTL+, a demand-based, page-level flash translation layer (FTL) that integrates learned-index- based translation with adaptive DRAM co-management to improve address translation efficiency in flash-based SSDs. LearnedFTL+ combines two complementary components under a fixed DRAM budget: a cached mapping table (CMT) for locality-rich accesses and a learned-index region for accesses where the CMT becomes ineffective. To make learned indexing practical for SSD address translation, we introduce three key techniques. First, an in-place-update linear model with a bitmap filter ensures that only trustworthy predictions are used for direct translation. Second, a virtual PPN (VPPN) representation constructs contiguous LPN-to-VPPN mappings without restricting physical placement. Third, group-based allocation, together with training assisted by sequential writes and GC, reduces model-training overhead. In addition, LearnedFTL+ supports eviction-driven model initialization and unified eviction across CMT entries and model segments, enabling adaptive DRAM co-management according to runtime access behavior. Experiments on a FEMU-based SSD prototype show that LearnedFTL+ improves throughput by up to 71.6% and reduces I/O latency by 11.9% on average, compared to state-of-the-art page-level FTLs.
Vision Transformers (ViTs) have demonstrated exceptional performance across various computer vision tasks. However, their susceptibility to adversarial white-box attacks poses a significant risk, especially in safety-critical applications. These attacks, with full model access, pose severe threat by drastically reducing accuracy. In response, we propose SAMURAI, a lightweight, preprocessing-based defense pipeline that mitigates adversarial perturbations without requiring model retraining or architectural changes. SAMURAI defends against adversarial inputs by applying a fixed sequence of four transformations: JPEG compression, resizing and center cropping, Gaussian smoothing, and normalization. This process disrupts adversarial attacks while preserving the semantic integrity of the image. Unlike computationally expensive defenses, SAMURAI introduces minimal overhead (e.g., 0.001× for ViT-Large), making it extremely lightweight for real-time deployment. Furthermore, our method generalizes effectively to other vision architectures, such as Convolutional Neural Networks (CNNs), demonstrating strong transferability. To support efficient deployment in resource-constrained environments, we also design a custom hardware accelerator for the SAMURAI pipeline that enables in-situ preprocessing within accelerators, effectively mitigating adversarial attacks. Experimental results show that SAMURAI achieves robust accuracy comparable to state-of-the-art while requiring only 0.009× the computational cost.
Disaggregated memory (DM) architectures enhance resource utilization and architectural scalability by separating computing and memory resources into distinct pools connected via high-speed interconnects, such as RDMA and CXL. Adaptive radix tree (ART) is a widely used range index known for its efficient support of variable-sized keys. However, traditional ART structures incur substantial network overhead in DM architectures during index traversal. In this paper, we propose Sphinx, a high-performance and cache-efficient ART for DM architectures. To minimize network roundtrips during index traversal, Sphinx employs Flat Inner Node Table to eliminate data dependencies among hierarchical ART nodes, enabling memory-level parallelism. Moreover, Sphinx introduces Succinct Filter Cache, which leverages a space-efficient cuckoo filter in the local cache of compute nodes to mitigate read amplification during index traversal. By further incorporating Semi Lock-free ART Nodes, Sphinx achieves high scalability with strong consistency guarantees. Experimental results show that Sphinx outperforms state-of-the-art counterparts by up to 7.3× in the YCSB benchmark.
Compiler-driven deployment has become a major source of model extraction risk in deep learning systems. Existing studies have shown that compiled binaries may still leak model structure and semantics, but most prior attacks implicitly focus on deployment regimes where graph structure remains relatively accessible. In contrast, the security implications of Ahead-of-Time (AOT) compiled models, which are increasingly important for resource-constrained edge deployment, remain underexplored. More importantly, AOT extraction is often formulated as a template-based abstract matching problem, while its primary difficulty lies elsewhere: compilation hides model semantics inside function–buffer interactions, memory reuse, and implicit execution dependencies. In this paper, we show that the significance of AOT model extraction lies not only in building a stronger attack, but also in revealing a more fundamental coupling between compilation and model recoverability. We argue that, in AOT binaries, the critical object that survives compilation is not merely an operator pattern, but the dependency structure shaped by compiler-managed execution and memory reuse. Based on this view, we propose ENNACE, a dependency-centric extraction framework that reconstructs hidden execution dependencies and then recovers fine-grained operator attributes from optimized AOT binaries. Extensive experiments show that our dependency-centric reformulation of AOT model extraction substantially strengthens attack capability, surpasses prior state-of-the-art methods, and offers practical guidance for both future attack design and defense development.
In this paper, we present a Differential Fault Attack (DFA) on the lightweight stream cipher Atom, proposed by Banik et al. in IACR Transactions on Symmetric Cryptography (TOSC)-2021. It employs two key filters simultaneously during the pseudo-random generation algorithm phase, one of which depends on LFSR state bits. Due to this LFSR-dependent key filter, the authors claim that forming algebraic equations relating key and state bits as variables to the keystream bits is difficult unless the entire LFSR state is known. In contrast, we propose a method to formulate such algebraic equations without guessing any LFSR bits. This enables us to implement a successful DFA on Atom. To the best of our knowledge, this is the first reported DFA on Atom. In the proposed DFA, we identify the location of injected faults using a weighted ensemble of trained MLP and XGBoost models. To further improve accuracy, we filter out ML predictions with confidence below a predefined threshold. We found that this strategy significantly reduces the number of SAT solver invocations and improves the overall time complexity of the attack. Based on our experiments, we demonstrate a successful DFA on Atom within a practical time by injecting 18 faults, provided all are correctly identified. Obtaining a set of 18 correctly identified faults requires, on average, 52 fault injections. The attack requires a total of 70 keystream bits (normal and faulty combined) just after a fault injection and guessing two random key bits.
Value Prediction is a long-standing technique to boost instruction-level parallelism by speculatively breaking data dependencies through predicting register-write values. Existing state-of-the-art predictors, such as EVES, combine computational and context-based approaches but still rely exclusively on local value history, limiting their ability to capture broader correlations. Global value prediction, which exploits correlations across multiple dynamic instructions, has been explored only sparingly. The gDiff predictor first demonstrated the potential of global stride correlations, and EgDiff recently improved upon it with practical refinements. However, both remain PC-localized and thus fail to exploit per-path correlations, where global correlations vary across execution paths. In this work, we propose CgDiff, the first context-based global value predictor. CgDiff augments stride-based global prediction with control-flow history to capture path-sensitive global correlations that elude existing designs. Our evaluation shows that a compact 8.92KB CgDiff not only surpasses a much larger 44KB EgDiff, but also outperforms the state-of-the-art EVES predictor in IPC speedup. Furthermore, a storage-efficient 16.92KB hybrid (CgDiff + EVES) achieves the highest performance among all predictors under comparable budgets. These results demonstrate that context-based global value prediction is a powerful and storage-efficient complement to existing local designs, opening a promising new direction for future research in value prediction.
Stochastic computing (SC) is an emerging computing paradigm known for its strong fault tolerance. To implement stochastic circuits with low hardware cost, state-of-the-art methods approximate a target function by a Bernstein polynomial and synthesize the corresponding circuit by properly assigning cubes, i.e., product terms, to realize the Bernstein polynomial. However, as the polynomial degree increases, cubes become larger and the solution space grows exponentially, rendering the existing methods impractical. To address this issue, we develop an optimized stochastic circuit synthesis method consisting of four key components: 1) an optimized method to quantize the coefficients of Bernstein polynomials for cube assignment, 2) an efficient solution space exploration method, 3) four acceleration techniques for solution space exploration, and 4) a constrained linear transformation technique that reduces the complexity of the function prior to synthesis. The experimental results show that compared to the state-of-the-art method, the proposed method reduces the area, delay, and area-delay product by 39.34%, 12.74%, and 45.09%, respectively. Moreover, the proposed method demonstrates high scalability by being able to synthesize Bernstein polynomials of degrees up to 42, a value unreachable by prior methods.
Persistent memory (PM) bridges the latency and cost gap between DRAM and SSDs. Within the DRAM–PM–SSD hierarchy, deploying key-value-separated key-value stores (KV-separated stores) is imperative for optimizing system longevity and performance. This architecture mitigates SSD write amplification and preserves PM endurance by minimizing writes. Existing KV-separated stores in the DRAM-SSD architecture, however, fail to fully exploit this three-tier hierarchy due to three issues. First, LSM-tree indexes incur high read amplification on PM. While learned indexes offer faster reads, they suffer from severe write-read asymmetry that can undermine overall efficiency in write-intensive workloads. Second, the lack of real-time invalid data identification delays space reclamation. Third, contemporary KV stores treat PM as a passive write buffer, underutilizing its low read latency under skewed workloads. To address the above issues, we propose PALIKV – a PMresident learned index-based KV store for the DRAM-PM-SSD hierarchy. We first design an adaptive two-level index that combines a PM learned index with a dynamic DRAM B+-tree buffer. This structure balances lookup efficiency with high write throughput while filtering redundant updates and extending PM lifespan. Second, the learned index enables real-time invalid data identification. This facilitates an expedited garbage collection with device-specific reclamation granularity, thereby significantly reducing space amplification. Third, a hotness-aware data placement proactively migrates warm data from SSD to PM, allowing PM to serve skewed reads and eliminating the latency-constrained SSD from the critical read path. The experimental results unveil that PALIKV significantly outperforms SOTA KV-separated stores and DRAM-PM-SSD KV stores in terms of throughput and latency.
Existing linear Byzantine fault-tolerant (BFT) protocols heavily rely on Threshold Signatures (TS) to reduce communication complexity. The threshold signatures used and implemented in these BFT protocols should be non-interactive and all such schemes rely on heavy pairing operations. Threshold signatures using no pairings such as Schnorr TS are computationally more efficient but require multiple rounds of interaction and lack robustness. There has been a long-standing question on whether one could build more efficient BFT protocols from such pairing-free signatures. In this paper, we develop a novel approach that allows using threshold signatures like Schnorr TS in linear BFT protocols in an effective manner. In this approach, we can significantly reduce the interaction overhead caused by Schnorr TS while maintaining its computational efficiency. We instantiate a HotStuff-style BFT protocol called ROPSCON and show that ROPSCON achieves up to 2.2× higher throughput compared to both HotStuff protocols using pairings as well as ones with directly aggregated signatures. The improvement is particularly evident in high-delay and lowbandwidth environments.
BCube, one of the representative server-centric data center networks, is of high practical value in high-performance computing clusters and large model distributed training. During the long-term operation of data centers, component failures have become commonplace, which easily lead to network partitions and service interruptions. Therefore, fault tolerance serves as the core foundation for guaranteeing service continuity and stable operation of data centers. Cycle structures are a critical topological foundation for network fault tolerance, as they provide redundant communication paths, enable deadlock-free parallel communication, and facilitate network load balancing. The capability of constructing valid cycles in faulty networks directly determines the resource utilization efficiency and service availability of data centers. In this work, we first develop a theoretical framework for cycle fault tolerance analysis in BCube and derive the exact value of its cyclic connectivity to evaluate the network’s capability to preserve cycles under node failures. On this basis, we propose a two-stage fault-tolerant cycle construction algorithm adapted to the structural characteristics of BCube. The first stage identifies the largest fault-free connected component containing cycles to define the effective region for cycle construction. In the second stage, multiple strategies are integrated to efficiently generate valid cycles within the component, while maximizing the coverage of available fault-free nodes. Experiments conducted on BCube networks of different scales under diverse fault scenarios verify that our algorithm achieves superior performance in terms of running efficiency and node coverage, as well as excellent scalability and fault robustness.
Quantum computing (QC) emulation is critical for exploring and advancing near-term quantum algorithms, given the ongoing scalability and reliability challenges of quantum hardware. While FPGA-based QC emulators have emerged as efficient alternatives to bridge the gap toward practical quantum computers, most existing solutions depend on high-performance systems, limiting their applicability in embedded and edge environments. In this work, we present a scalable, standalone FPGA-based emulator specialized for resource-constrained systems. Our design targets the Quantum Approximate Optimization Algorithm (QAOA), particularly for the Weighted-MaxCut problem. By leveraging diagonal decomposition and a pipeline-centric hardware architecture, we reduce the computational complexity of QAOA from O(N2) to O(N), where N=2n is the state dimension for n qubits. This reformulation and its architectural codesign significantly reduces hardware overhead, enabling larger qubit configurations on edge-level FPGAs. We encapsulate these optimizations into a hardware accelerator called the Quantum MaxCut Accelerator (QMA), which integrates seamlessly into a RISC-V platform, forming a self-contained emulator. Additionally, we introduce QC Emulator eXpress (QEX), a full-stack automation framework that streamlines QMA integration into configurable RISC-V platforms, significantly facilitating rapid and scalable emulator development and deployment. Through extensive prototyping of various QAOA emulators, our experiments confirm that the proposed QMA achieves energy reductions of up to 907× compared to the CPU-only software baseline under the same standalone FPGA/RISC-V setting and reliably supports up to 9 qubits on a mid-tier FPGA. These results demonstrate the energy efficiency and scalability of the proposed system as a self-contained FPGA/RISC-V platform for edge-local QAOA emulation, prototyping, and HW/SW co-design exploration under resource-constrained conditions.
As a key 5G enabler, edge computing locates resources near users to enable low-latency services, and microser-vices architecture (MSA) decomposes monolithic services into microservices, easing deployment and scaling of mission-critical applications with high reliability requirements. Existing studies on microservice backup and deployment often adopt dedicated backup strategies, resulting in excessive redundancy and high resource consumption. This paper investigates reliable service deployment with shared backups in resource-constrained and dynamic edge environments, aiming to meet differentiated reliability requirements while optimizing resource efficiency. However, shared backups introduce interdependencies among services, complicating relationships among backup and deployment strategies, service reliability, resource costs, and loads. To model these intricate relationships, we divide microservices (service functions) of the same type into service function groups for sharing backups and formulate the problem as an integer nonlinear programming problem, proving its complexity. Moreover, the sequential arrival of requests in dynamic environments renders this problem a multi-stage decision problem, with high-dimensional resource constraints and a large-scale solution space adding complexity. Thus, we design a deep reinforcement learning (DRL)-based shared backup scheme with theoretical guarantees, which leverages DRL to capture long-term rewards and generate fractional solutions, while domain knowledge—specifically, the insight that providing additional backups to service function groups with low reliability yields greater reliability improvements—is used to adjust the fractional solutions. This adjustment helps prevent the DRL agent from falling into poor local optima and violating constraints. Finally, extensive experiments on real-world Alibaba traces show our method reduces costs by up to 70.52% compared to state-of-the-art approaches.
Serverless functions run event-driven code on demand without long-lived servers, which makes them a good fit for dynamic, latency-sensitive edge workloads. However, when a function is invoked for the first time or after idling, the platform must initialize a container and load runtimes and libraries, incurring a cold start delay that can reach hundreds of milliseconds to seconds. The effect is amplified by resource-constrained, bursty edge environments. Existing mitigations include container reuse, prewarming, and fixed retention. These methods help, but still suffer from limited reuse across functions, largely static strategies, and costly real-time decisions. To address these challenges, we propose a layered container framework called Feedback-Aware Hierarchical Edge Scheduler ,(FAHES). It uses Zygote containers to share dependencies across functions and supports dynamic warm pool management, significantly reducing startup latency and memory overhead. To enable dynamic container resource allocation for real-time scheduling, FAHES employs Hidden Markov Models (HMMs) to predict short-term function invocations. FAHES further integrates adversarial and stochastic algorithms to capture system dynamics and make efficient scheduling decisions. We prove that FAHES achieves sublinear regret in scheduling performance. Simulation-based experiments on an edge cluster show that FAHES reduces the overall cost by up to 60.5% compared to state-of-the-art baselines.
Serverless computing is gaining popularity, and serverless workflows stand out as its key workload form. Since resource configurations in serverless workflows are typically manually specified, considerable research has focused on automating resource allocation optimization. However, conventional studies generally follow a coupled CPU–memory allocation, thereby limiting cost-effectiveness, or assume that accurate function performance profiles are known in advance. Moreover, they do not explicitly address the impact of function cold starts on workflow performance. To address these limitations, this paper introduces a serverless workflow provisioning model that jointly supports decoupled resource allocation and function container reuse among workflow tasks implementing identical functionality. Based on this model, we propose a structure-aware trust-region Bayesian optimization (STBO) method to optimize resource configurations for minimizing cost under deadline constraints. The proposed approach is implemented in OpenWhisk, and evaluation experiments demonstrate that, compared with traditional methods, STBO increases the constraint satisfaction rate and reduces execution cost by over 17% on average.
