In our envisioned "Chang's Next Paradigm of New Space", Commercial-Off-The-Shelf (COTS) systems (embodying multiple COTS ICs, vis-a-vis individual COTS ICs) are employed in space applications. As the majority of COTS ICs are susceptible to radiation effects, particularly MicroSingle-Event-Latchups (mu- SELs) and SELs, COTS systems are likewise vulnerable. We had proposed a protection means involving the deployment of an AI-based mu-SEL/SEL detection on the input power rail (external to the COTS system) - hence, without needing physical modification to the COTS system. However, the input power rail's R/C/L configuration, which varies across different COTS systems, obscures mu-SEL/SEL characteristics, thereby degrading detection accuracy. In this paper, we propose an improved AI-based mu-SEL/SEL detection approach that integrates R/C/L- aware data augmentation and temporal feature extraction to improve its robustness against R/C/L-induced distortions. We achieve high (86.6%) detection accuracy across different R/C/L configurations - improving by 23.4%-73.5% over prior works. Our proposed approach is hence appropriate for space applications, facilitating our said envisioned "Chang's Next Paradigm of New Space".
This paper presents the development and validation of a compact point-of-care (POC) device that integrates homogeneous heating with fluorescence-based detection for loop-mediated isothermal amplification (LAMP) on microfluidic platforms for the diagnosis of tuberculosis (TB). A copper thinfilm microheater controlled by a proportional-integral-derivative (PID) algorithm enables rapid heating to 65 degrees C within one minute and maintains thermal stability within +/- 1 degrees C over an hourlong period. Thermal imaging and histogram analysis confirm temperature uniformity, with over 97.6% of readings falling within 64.5-65.5 degrees C, and the system demonstrates rapid recovery when a microfluidic thermal load is applied. The fluorescence detection module, using AS7343 spectral sensors and blue light-emitting diodes (LED) for excitation, was evaluated using LAMP mixes of two gene targets, gyrA and atpE for M. tuberculosis. Fluorescence readings effectively distinguished positive and negative samples using a threshold of 469 relative fluorescence units (RFUs). The results closely match those obtained using agarose gel electrophoresis and ultraviolet (UV)-based visual inspection. By combining precise thermal control and fluorescence detection on a single electronics platform, this system offers a streamlined solution for accurate, low-cost molecular diagnostics in resource-limited or field-based settings.
This paper presents the design and measurement results for a wideband SiGe front-end module operating from 24.25 GHz to 30.5 GHz, which integrates a passive phase shifter (PS), a variable gain and phase-inversion amplifier (VGA) with low impedance and minimal phase variation, and a linear power amplifier (PA) designed for beamforming systems. The PS with the VGA provides a full 360 degrees tuning with a resolution of 5.6 degrees, while the gain control spans 17 dB in 0.5 dB increments. Measurements present a maximum gain of 27 dB, P-sat of 21 dBm, PAE(max) of 31.2% at 27 GHz. Developed with 130nm SiGe BiCMOS technology, the circuit occupies an area of 0.53mm(2) excluding pads.
This paper presents a novel adaptive equalization system integrated into the phase detector of a clock and data recovery (CDR) circuit to reduce hardware complexity. The proposed inter-symbol-interference (ISI) detector extracts equalization feedback directly from the bang-bang phase detector (BBPD) using simple bit-level logic, eliminating the need for conventional adaptation. A hybrid half-rate BBPD enables high-speed operation, while a current-mode capacitance multiplication technique reduces the filter area. The design is fabricated by TSMC 90 nm (TN90GUTM) 1P9M CMOS process with a 1.0 V supply. Operating at 5 Gb/s, the CDR achieves a 2.5 GHz recovered clock with 15.56 ps peak-to-peak jitter and 2.27 ps RMS jitter. The total power consumption is 21.9 mW, with 15.1 mW for the CDR and 6.8 mW for the adaptive equalizer (EQ). The chip area is 1.38 mm(2), and the core area is only 0.13 mm(2). This architecture achieves a compact, low-power, area-efficient solution suitable for high-speed serial receiver (Rx) and can be widely applied to channel loss conditions ranging from 0 dB to 18 dB.
Automated optimization of operational amplifiers is a complex task that demands efficient methods. This paper presents a compact, open-source reinforcement learning approach for op-amp optimization within the IHP SG13G2 process. Our approach adopts and compares the TD3 and SAC algorithms against DDPG, showcasing more reliable learning and faster progression. Using a compact MLP rather than a GNN for the agent reduces complexity and computing effort, while still achieving competitive results. The proposed framework makes use of the gm/Id design method as the primary state input for the RL agent, thereby effectively embedding well-known analog design principles to improve guidance. We also apply online normalization to the agent inputs, thus enhancing stability and significantly reducing the initial random search phase. Reward functions are specifically designed to address op-amp performance metrics. Findings from an experimental folded-cascode optimization study demonstrate that, compared to DDPG-based methods, convergence is rapid and learning rates are stable. Compared to prior GNN-based RL approaches, our lightweight framework offers improved usability, reproducibility, and accessibility as an open-source tool.
The use of accelerated radiation testing is an invaluable tool for studying the behavior of computing systems under radiation effects. Despite the existence of relevant testing guidelines and standards, there are currently few published works dedicated to detailing methods for performing accelerated radiation tests on processor-based computing systems. This paper delineates the current form of the MultiRad project's testing method, as well as the rationale behind its design. After continuous improvements and modifications since its inception in 2020, it has been used to test various computing systems - from resource-constrained 8-bit microcontrollers to highly capable 64bit computers - under 14-MeV and thermal neutrons and can be quickly implemented for other computing system platforms. Notably, variations of the presented method have supported and enabled the publishing of 17 journal articles and 25 presentations in international conferences.
Dynamic comparators are critical components in analog-to-digital converters (ADCs), yet their reliability can be severely compromised by Single-Event Transients (SETs) in radiation environments. This work presents a comparative study of SET susceptibility across prominent dynamic comparator architectures, including the StrongArm latch and Double-Tail structures, with emphasis on the effectiveness of the Triple Modular Redundancy (TMR) mitigation technique. To further improve radiation resilience, we propose a Radiation-Hardened-by-Design (RHBD) dynamic comparator based on a modified StrongArm architecture, termed the StrongArm Quatro-Latch comparator. The proposed design incorporates structural enhancements aimed at suppressing SET-induced disruptions. Circuit-level simulations demonstrate that the Quatro-Latch architecture significantly improves SET tolerance while maintaining competitive performance in terms of speed, power, and area. Comparative analysis across all architectures provides insight into trade-offs between SET robustness and design metrics, confirming the proposed RHBD comparator as a compelling solution for dynamic comparator-based ADCs operating in radiation-prone environments.
We present a portable, low-cost microfluidic impedance platform for rapid phenotypic antimicrobial susceptibility testing (AST). The system computes a calibration-free relative impedance metric (Delta_rel = V(0)/V(t) - 1) from real-time voltage ratios to distinguish bacterial growth from antibiotic inhibition within 60 minutes (n = 6). Using only 100 mu L samples and open-source electronics, the platform achieves submillivolt precision at a total cost below $50. Compared with conventional culture-based AST (> 18 h), this approach provides a 15-20x reduction in diagnostic time, supporting decentralized, point-ofcare applications in resource-limited settings.
This work presents a low-power analog integrated image edge detector based on squarer and threshold circuits. A hardware-efficient approximation of the Robert’s Cross operator forms the core of the design, which can be scaled for different image resolutions and used as a building block for biomedical engineering concepts. The proposed edge detector consumes only 19 nW per pixel, achieves an average PSNR of 26.9 dB and SSIM of 0.84, and supports high computational throughput of 190000 fps. Robustness is verified through Monte Carlo simulations, process variation analysis, and corner-case testing. Comparative results with software-based edge detectors confirm the design’s accuracy and reliability. The simulations are performed using Cadence IC Suite in a 65 nm CMOS process, demonstrating its suitability for low-power, high-speed image processing applications.
In this paper, we present a novel accumulator architecture optimized for applications requiring a large number of guard bits, such as Cascaded Integrator-Comb (CIC) filters. Our approach leverages the disparity between the dynamic range of the input signal and the accumulator register by dividing the architecture into three sub-circuits: a high-speed LSB accumulator, a low-power increment evaluator, and a slow-speed MSB accumulator. This partitioning significantly reduces switching activity and clock frequency for MSB computation, resulting in improvements in power-delay-product and areadelay-product.
This paper presents a comparative analysis of two ultra-low-power, two-stage operational transconductance amplifiers (OTAs) designed for subthreshold MOS operation and employing a self-cascode topology to achieve very high DC gain. The first OTA uses a bulk-driven (BD) input stage and operates with a 400-mV supply, while the second adopts a gate-driven (GD) approach, incorporating an additional tail-current transistor to bias the differential pair, and thus requires a 500mV supply. Analytical modeling and simulation results are used to assess the trade-offs between the two architectures in terms of main performance parameters. In particular, the expected disadvantages in dc gain and gain-bandwidth for BD OTAs are found to be less severe than typically assumed, while their smaller required compensation capacitor enables improved Slew Rate. Noise performance remains a major drawback.
Liquid neural networks are well-suited for modeling data with rich temporal dynamics across multiple timescales. Enabling them to be deployed on edge devices demands a high energy efficiency. This work presents the Spiking Liquid TimeConstant Network (sLTC), a novel model combining adaptive time constants from Liquid Time-Constant (LTC) neurons with the sparse activity of Spiking Neural Networks (SNNs). The sLTC reduces energy consumption by up to 9:22x compared to LTC and outperforms it in terms of accuracy on event-driven datasets. It also surpasses the Liquid State Machine (LSM) on most benchmarks.
State-of-the-art layout-aware synthesis methods for analog integrated circuits (ICs) rely extensively on off-theshelf layout extractions and post-layout simulations to assess the circuits' functional behavior, incurring prohibitive optimization time. To address this challenge, this paper proposes the development of a novel post-layout performance regressor based on deep learning (DL) models. Specifically, convolutional variational autoencoders (CVAEs) are applied for unsupervised feature extraction from analog layouts, producing a latent space. Then, a collection of artificial neural networks (ANNs) conducts performance estimation directly from the lowerdimensional space. By the usage of convolutional layers to deal with analog IC layouts, the model learns the underlying impact of the floorplan and interconnects on the functional behavior of the circuit. Preliminary results reveal mean absolute percentage errors (MAPEs) below 2% for different performance metrics of a typical analog structure, with the model inference requiring only 3.9 milliseconds, about 3,000x faster than the full parasitic extraction and simulation.
In this paper, we present a wide-swing input output (0.15/0.75 V input dynamic range) buffer with a closed-loop current regulator for a 7-bit Digital-to-Analog (D-to-A) converter implemented in 28 nm CMOS technology for applications in pixel detectors in High Luminosity Large Hadron Collider (HL-LHC). The key stringent point of the proposed D-to-A Converter is to manage a very large input dynamic range (0.15/0.75 V) while using Standard Process (SP) MOS transistors (MOST) in 28 nm CMOS at 0.9 V supply voltage. The D-to-A converter employs a voltage-mode R-2R resistive-ladder topology. The R2R voltage (proportional to the digital input code) is buffered to the output by means of an advanced Operational Amplifier (OP-AMP) in closed-loop Voltage Follower configuration. The OP-AMP features: a complementary (p/n MOST) input differential pair for rail-to-rail dynamic, voltage controlled current generator circuit to compensate for process temperature and radiation effects, and an inverter-based class-AB output stage for driving the output load. The proposed buffer and D-to-A has been extensively simulated in both nominal conditions and under Process-Voltage-Temperature variations and Total Ionizing Dose (TID), achieving a Differential and Integral Non-Linearity lower than +/- 0.5 LSB.
We introduce a simulation-driven methodology to assess the Single Event Effect (SEE) sensitivity of CubeSat electronics under mission-specific radiation environments. By combining component-level Single Event Upset (SEU) crosssection data with detailed 3D structural shielding models, our approach enables fine-grained estimation of SEE rates. Applied to the RAMSES CubeSat mission, it demonstrates that accounting for 3D analysis reduce predicted SEU rates by over 50x compared to simplified standalone models. This improved precision enhances component selection, informs shielding strategies, and streamlines fault mitigation planning, ultimately supporting costeffective and reliable mission design.
Understanding the potential failure modes of digital circuits is fundamental to implement effective protection mitigations. This work presents a sub-classification of events based on their failure modes and a characterization methodology to classify the observed events. The characterization is performed through fault injection campaigns on representative hardware designs, enabling a thorough evaluation of circuit behavior and reliability under various fault conditions. The developed framework provides valuable insights into the development and validation of mitigation strategies. To support this analysis, an ElectroMagnetic Fault Injection (EMFI) setup was designed and used to carry out the characterization and test different mitigation strategies.
Dependency on software technologies or hybrid systems in computer vision systems lacks integrability on chips. It also suffers from insufficient throughput for real-time processing, which is critical for autonomous driving. This paper proposes a pure-hardware computer vision system based on the state-of-the-art YOLO algorithm, specifically LPYOLO. All the network operations as well as the essential post-processing are purely hardware implemented. To the author's knowledge, this is the first software-independent YOLO inference. The FINN framework is used to build the main intellectual property (IP) core of the network. The post-processing module (PPM) for the neural network's raw output is implemented using Verilog HDL. The system introduces an inference rate of about 67 fps on the ZCU102 FPGA board. It provides reliable results with mAP50 0.84 and mAP50-95 0.34 upon being trained on the car detection Kaggle dataset. The quantization bit precision is 4W4A. Moreover, the overall system consumed 16.7% from the ZCU102 LUTs.
This work compares two modern optimization approaches for analog integrated circuit sizing: evolutionary algorithms (EAs) and reinforcement learning (RL). While EAs have demonstrated consistent performance with minimal configuration effort, RL offers a data-driven alternative that can learn adaptive strategies through interaction. Both methods are evaluated within a unified framework that accounts for multiple process, voltage, and temperature (PVT) corners. The comparison highlights differences in efficiency, convergence behavior, and generalization capability. Results aim to clarify the strengths and limitations of each approach and guide their applicability in automated analog design.
This paper presents a multichannel CMOS boxcar averager specifically designed for broadband Pump-Probe spectroscopy, an advanced optical technique largely used in material science and biology to study ultrafast phenomena on the fs-ps timescale. The ASIC features low-noise switched capacitor integrators able to average up to 1023 pump-probe pulses with a repetition rate of 1MHz, enabling the achievement of an overall equivalent noise below 1 ppm relative to the mean optical power, as required by the most demanding pump-probe experiments. The chip operates with 20 channels in parallel for processing multiple wavelengths simultaneously, accelerating the acquisition of optical spectra. The combination of sub-ppm resolution and microsecond operation are well beyond the current state-of-the-art solutions for pump-probe spectroscopy, which typically operate at only a few kHz for similar resolution.
Data poisoning attacks, which subtly corrupt training data, pose a significant risk to medical image classification, potentially leading to severe diagnostic errors. Existing defenses often rely on full access to training datasets and manual sanitization, which are inefficient and inadequate for complex medical images, particularly when the poisoning is minimal. To tackle this, we propose an Explainable AI (XAI)-based approach using Layer-Wise Relevance Propagation (LRP) to detect poisoning in ResNet-101 models trained on chest X-rays with healthy and pneumonia subjects. Specifically, LRP outcomes provide justifications for how the ResNet-101 model classifies certain images as pneumonia. Illogical justifications from LRP outcomes, along with inconsistencies between decisions and justifications, can indicate the presence of poisoned data in the trained models. By analyzing LRP-generated heatmaps and extracted features (e.g., SIFT, HOG), we train a classifier to distinguish between models trained on clean and poisoned data. Our method achieves an AUC of 0.86 even with a small amount of poisoned data, requiring no access to the training dataset. Using only a few test input images, it demonstrates the potential of explainability-driven features in identifying poisoned models.
