The turn-on behavior of high voltage ESD devices is studied during HBM ESD stress. Two phenomena are experimentally observed for two different HV processes and several device architectures: a voltage overshoot up to two times of the TLP triggering voltage, and a current overshoot several times the nominal HBM current.

The new measurement methodology allows extracting guard ring efficiency under ESD stress conditions. A new figure of merit to design latch-up protection around ESD protection structures is defined and showed that an optimal sizing of critical dimension can be achieved to enhanced ESD protection levels. The efficiency of the approach opens a new area to study latch-up guard ring design with respect to ESD stress conditions. The methodology could be used to address the impact of technology parameters like STI depth, doping profiles and is generic enough to be applied to any kind of ESD protection strategies and devices

HBM testers are tools for ESD product qualification whereas TLP testers are used for device characterization. The ability to extract TLP-like IV curves from an HBM system is demonstrated in this paper. Together with measurement results on wafer-level, the full methodology is presented and compared to standard 100 ns TLP measurements. The advantage of this methodology is that the quasi-static characteristic of a ESD protection device can be obtained much faster and with only one test procedure.

A systematic implementation of ESD protection for a 17GHz LNA in 130nm SiGeC BiCMOS technology is presented. The ability to achieve pre-silicon ESD reliability confidence is demonstrated through the comparison of HBM ESD simulations and measurements on the circuit. The inductor-based ESD protection methodology achieves more than 6kV HBM ESD robustness for the LNA, the highest ever reported in a similar technology.

This paper addresses the ESD reliability issues in RFICs, focusing on the technology impact on the device and design. We also present the basic RF ESD protection methods used in industry. Presents the general topology of a 5 GHz LNA, which is protected using several ESD protection methodologies, and describes the 90 nm CMOS process technology used for the fabrication of the LNA. The measurement procedures used for the evaluation of stand-alone devices and LNAs are described. The ESD performance of standard ESD protection devices is reviewed and presents results and discussions on the ESD reliability of various ESD protection methods employed from the device point of view, followed by an outlook on the future RF ESD challenges, and conclusions.

ESD protection strategies utilized in RF circuit applications in CMOS and BiCMOS technologies are investigated and the results are presented in this paper. The conventional approach using diodes with power clamp is compared with novel approaches such as plug-and-play passive elements and full or partial circuit-ESD co-design. The trade-offs are discussed from both RF and ESD point of views. Common problems as parasitic ESD current discharge paths and voltage overshoot are discussed and solutions are proposed