A chip-scale optical transceiver was developed based on silicon photonics technology and optical/electrical assembly for 25-Gbs× four-channel applications. Optical transmitters and receivers were integrated on a single silicon platform enabled by the hybrid integration of a quantum-dot laser diode, optical pins, and a 28-nm CMOS based electrical IC. Temperature compensation functions were implemented in a modulator driver and a transimpedance amplifier for high-temperature operations. The functions allowed us to successfully demonstrate error-free 25 Gb/s × four -channel data transmission at 85°C.

High integration of photonics circuits and electronic circuits is expected in Si photonics technology. The small size of integrated photonics circuits is expected to lead to low costs and high-density optical interconnection. On the other hand, reduction in packaging costs will become vital toward lowering costs because of the demand for highly accurate assembly processes in optical coupling. Harmony between integrated devices and packaging design should be consider to realize miniature size and low cost transceiver. We propose advanced devices and Packaging of an Si-photonics-based optical transceiver for optical interconnection.

Infrared light detection capability of a hydrogenated amorphous silicon waveguide with a vertically stacked pin structure by utilising defect absorption, i.e. transition between dangling bond defect and extended states is demonstrated. The responsivities for a 0.6 mm-long device are approximate to 6.2 and approximate to 0.22 mA/W at 1300 and 1550 nm wavelength, respectively.

To implement a large-scale integration of superconducting quantum bits (qubits), we have investigated a process of fabricating submicrometer Al/AlOx/Al trilayer Josephson junctions. Moreover, on the basis of this process, we developed a means of fabricating different kinds of superconducting qubits. Superconducting qubits require not only small junctions, but also peripheral circuit elements, such as a large resonator, on the same chip. As a result, we chose to use planarization in the self-aligned junction contact formation, which suppressed a pattern-area-dependence of the chemical-mechanical polishing rate. In addition, Al fine wires with a width of 0.2 μm were required in some parts of the qubits to increase the coupling strength between the SQUIDs and qubits. We developed a two-step etching process to form such fine wires using i-line photoresist, which had a high etching resistance. The operation of three-junction flux qubits was confirmed in a dilution refrigerator.

Interposers for inter-chip interconnects should perform stably under high-temperature conditions and rapid temperature change due to the heat generated by mounted large-scale integration (LSI) chips. Athermal silicon optical interposers integrated with quantum dot lasers and other temperature-insensitive components on a single silicon substrate are demonstrated, and error-free data links at 12.5 Gbit/s operating from 25 to 125 degrees C are achieved without any bias adjustment. Since maximum junction temperatures in most LSIs have been below 125 degrees C now and will be in the future, the interposers are tolerant of heat generated by LSIs, and are suitable for inter-chip interconnects.

We developed a high speed and high efficiency MOS (metal-oxide-semiconductor)-capacitor type Si optical modulator (Si-MOD). We designed the optimum Si-MOD structure and demonstrated a very high modulation efficiency of 0.28-0.30 Vcm, which is one of the most efficient in Si-MODs with MOS junctions. We also demonstrated a high speed of 25 Gbps for the Si-MOD integrated with a Ge photodetector (Ge-PD), and also high-speed operation of 15 Gbps with 65nm CMOS driver at 1.3 m wavelength.

We developed a 25-Gb/s silicon modulator with 9.83-dB.V alpha V L-pi, which is smallest of those operated at 25 Gb/s and higher. We used forward-biased diode operations, which enables small V L-pi with moderately doped low-loss waveguides.

We developed a high speed and high efficiency Si optical modulator (Si-MOD) with a metal-oxide-semiconductor (MOS) junction by applying the low optical loss and low resistivity of the poly-Si gate. We designed the optimum Si-MOD structure and demonstrated a very high modulation efficiency of 0.28-0.30 Vcm, which is one of the most efficient in Si-MODs with MOS junctions. We also demonstrated a high speed of 15-25 Gbps for the Si-MOD for both the 1.55 μm and 1.3 μm wavelengths.

A Si wire arrayed waveguide grating designed to reduce the noise and transmission peak width and avoid systematic phase error generated at the curved waveguides is reported. A slab waveguide structure to remove stray light is used. 200 GHz spacing 16 channel devices were fabricated by ArF immersion. An improved crosstalk of -23 dB was obtained.

An Si wire array waveguide grating wavelength demultiplexer fabricated using immersion ArF lithography is reported. The tilt directions of the input and output star couplers are aligned in the same direction to avoid phase error generated at the curved waveguides. A 16 channel device with 200 GHz wavelength spacing was fabricated.

We report the design of the Mach-Zehnder interferometer wavelength filter using multiple Si waveguide structure sections. Tolerance to width error, temperature shift and polarization independence can be attained.

We developed a high-speed Mach-Zehnder modulator with the shortest phase shifter (100-μm length) reported so far. Our modulator exhibited 25-Gbps eye-openings with an extinction ratio of 4.3 dB and on-chip insertion loss of 4.7 dB.

1 Institute for Photonics-Electronics Convergence System Technology (PECST) 2 Photonics Electronics Technology Research Association (PETRA), West 7 SCR, 16-1, Onogawa, Tsukuba, Ibaraki 305-8569, Japan 3 National Institute of Advanced Industrial Science and Technology (AIST), West 7 SCR, 16-1, Onogawa, Tsukuba, Ibaraki 305-8569, Japan 4 Institute of Industrial Science, The University of Tokyo, 4-6-1, Komaba, Meguro, Tokyo 153-8505, Japan Phone: +81-29-868-6520 E-mail: j-fujikata@petra-jp.org

Thin films of (BaxSrJ−x)TiO3 (BST) deposited by RF sputtering have been studied for the application to the capacitor material of dynamic random access memory (DRAM). The effects of film structures on the dielectric constant and the leakage current were investigated. The films deposited at 550–600 °C consist of granular grains, and the films deposited above 650 °C contain columnar grains. The dielectric constant is related to the grain size in the direction of thickness. The leakage current increases as the film structure changes from granular to columnar. The low leakage current (less than 10−8 A/cm2 at +2 and −2 V) and the small value of equivalent SiO2 thickness (0.9 nm) were attained in the (Ba0.65Sr0.35) TiO3 thin films.