Effective work function (@f"m","e"f"f) values of Hf"x Ru"1"-"x alloy gate electrodes on SiO"2 metal-oxide-semiconductor (MOS) capacitors were carefully examined to assess whether the @f"m","e"f"f was determined by the crystalline structure or the composition of the Hf"xRu"1"-"x alloy. X-ray diffraction results indicated that the crystalline structures of Hf"xRu"1"-"x alloy were divided into hexagonal-Ru, cubic-HfRu or hexagonal-Hf with the increase of Hf content. The @f"m","e"f"f values could be controlled continuously from 4.6 to 4.0eV by changing the Hf content. The experimental @f"m","e"f"f value showed a good agreement with theoretical results considering the compositional ratio of pure Hf and Ru. These results suggest that the @f"m","e"f"f of Hf"xRu"1"-"x alloy gates on SiO"2 MOS capacitors is dominantly determined by the Hf"xRu"1"-"x composition rather than the crystalline structure.

In this paper, we have investigated the correlation between released hydrogen from Si/SiO2 interface and trap creation in bulk SiO2. The key point of these experiments is that hydrogen release from the interface is performed without trap creation in bulk SiO2 by injected hot carriers. Therefore, negative bias temperature (NBT) stress or substrate hot electron (SHE) stress was utilized to release hydrogen from Si/SiO2 interface. As a result, SILC is clearly observed after low voltage NBT stress in pMOSFETs. In this stress condition, impact ionization at anode interface due to injected hot electrons was negligible. In the same way, SILC is also observed by applying SHE stress in nMOSFETs. In addition, the SILC is suppressed by decreasing released hydrogen using fluorine incorporation in both stress conditions. From these results, we inferred that the released hydrogen from Si/SiO2 interface strongly correlates to the trap creation in gate oxides

Effective work function (φm,eff) values of Ru gate electrode on SiO2 and HfO2 MOS capacitors were carefully examined and discussed from the viewpoint of an effect of oxygen incorporation in Ru gate electrode on φm,eff. Annealing at 400°C in the reduction (3%H2) and the oxidation (1%O2) ambient resulted in similar changes in the φm,eff of Ru/HfO2/SiO2 and Ru/SiO2 MOS capacitors. Furthermore, the Ru gate MOS capacitor after annealing in the oxidation condition have shown almost the same φm,eff value to that of RuO2 gate MOS capacitors. The oxygen concentration in the Ru/HfO2 interface after annealing in oxidizing atmosphere is approximately one order of magnitude higher than that after annealing in reducing atmosphere as confirmed by secondary ion mass spectroscopy analysis. Furthermore, the higher oxygen concentration at the Ru/dielectric interface leads to the higher φm,eff value, regardless of SiO2 or HfO2 dielectrics. This indicates that φm,eff of Ru gate MOS capacitor is dominantly determined by the oxygen concentration at the Ru/dielectric layer interface rather than the dipoles originated from the oxygen vacancy in HfO2.

Self-organized (111) faceted NiSi 2 source and drain structure with segregated dopants in the NiSi 2 /Si interfaces has been proposed for aggressively scaled SOI MOSFETs. The advantages of this source and drain structure are a superior short-channel effect (SCE) immunity and a very small parasitic resistance. The SCE is suppressed by a trapezoidal shape of the channel and by a small variation in the channel length that is obtained thanks to the epitaxial growth of NiSi 2 on Si. The significant effects of the channel shape and the variation-free channel length are also confirmed by the numerical simulation. Owing to the low-temperature annealing at 600degC for NiSi 2 formation and dopants activation, wider selections of gate metal and high-k gate dielectric are possible. Moreover, NiSi 2 is the most Si-rich phase among nickel silicides family and thermally stable. Self-organized (111) faceted NiSi 2 source/drain structure is thus quite promising for future CMOS devices

In this work, the influence of direct-tunneling gate current on negative bias temperature instability (NBTI) was investigated using p/sup +/-gate and n/sup +/-gate/pMOSFETs having ultra-thin SiON films as gate dielectrics. As a result, it was found that an electron energy injected from the gate electrode does not affect on a threshold voltage shift (/spl Delta/V/sub TH/) and an interface-state generation (/spl Delta/I/sub CP/). However, the correlation between NBT degradation and the gate leakage current was observed, irrespective of the gate electrode type. This result suggests that the fluence of injected carriers has an effect on NBT degradation in the case of ultra-thin gate dielectrics.

Fully silicided platinum gates have been proposed as metal gate electrodes for scaled complementary metal oxide semiconductor field-effect transistors (CMOSFETs). The Pt monosilicide (PtSi) phase was formed on gate dielectrics by a full silicidation reaction at 400°C. PtSi gate electrodes on SiO2 possess a high effective work function of 4.9 eV, which could be used as a possible metal gate electrode for p-MOSFETs, while at the PtSi/HfO2 interface, Fermi-level pinning is observed independent of the PtSi fabrication process. The Fermi-level pinning at the PtSi/HfO2 interface is comparable to that at the poly-Si/HfO2 interface, and Fermi-level pinning does not occur at the Pt/HfO2 interface. These results show that Fermi-level pinning is induced by the presence of silicon atoms at the HfO2 upper interface.

Threshold voltage (V/sub th/) tuning by controlling Fermi-level pinning (FLP) position on HfAlO/sub x/(N) high-k dielectrics is demonstrated for CMOSFETs. Two kinds of methods for the effective work function tuning have been proposed. One is to control the Al concentration ([Al]) in the top interface of HfAlO/sub x/(N) to modulate the FLP position. The other is the doping into the PtSi/sub x<1.0/ (partial silicide: PASI) gates on HfAlO/sub x/(N) dielectrics. Symmetrical V/sub th/ values are obtained for the cases of poly-Si gate and FUSI (foil silicide)-NiSi gate n- and p-MOSFETs when the Al concentration is controlled in HfAlO/sub x/(N).

Degradation mechanism of stacked high-k gate dielectrics has been studied with metal-oxide-semiconductor capacitors having HfAlOX∕SiO2 films of various thickness combinations. A large leakage current with a peaked shape, named as the low-voltage peak current (LVPC), has been observed in the low-voltage region even in the initial current–voltage characteristics. It has been shown that a main part of LVPC is the transient current component controlled by the process of hole injection to traps in the vicinity of the HfAlOX∕SiO2 interface through the interfacial SiO2 layer. By the electrical stress, both the transient and the steady-state current components monotonically increase with time having different rates. Steady-state component has significantly larger rate than the transient component, and the same rate with the stress-induced leakage current (SILC) observed in the high-voltage region, indicating that the steady-state component of LVPC should be regarded as the SILC in the higher-voltage region extending down to the lower gate voltage region where the LVPC is observed.

We have demonstrated that the TDDB reliability should be predicted with the trap generation rate extracted with excluding the amount of initial traps and that the initial trap cannot explain the low Weibull slope P observed in high-k stacks.

There are a number of challenges against an actual employment of high-k films in the production, but ultra-thin SiON films cannot survive for low power application anymore. On the other hand, any new materials introduced into ULSI fabrication processes are required to be used for a couple of device generations, so the material selection should be carefully made. We have investigated HfAlON film as a high-k material in perspective of the equivalent oxide thickness (EOT)=1nm, and has newly developed a layer-by-layer deposition and annealing (LL-D&A) method for the film growth technique and a high temperature oxygen annealing (HiTOA) for the post-deposition annealing process, in order to overcome intrinsic challenges of deposited films. This paper describes recent progress of HfAlON gate stack technology, and discusses advantages of those approaches for advanced low power CMOS from scalability viewpoints of material and film growth technique as well as from experimental results of gate leakage current reduction, mobility improvement and threshold voltage control.

The carrier conduction and the degradation mechanism in n+gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlOX (Hf: 60at.%, Al: 40at.%)/SiO2 dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150°C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO2 layer (IL) thickness increases in a fixed high-k layer thickness (Thigh-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO2/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3nm, the hole current is dominant in the leakage current, regardless of Thigh-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n+poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n+poly-Si gate. Both the defect generation rate and the defect size in the HfAlOX/SiO2 stacks are large compared with those in SiO2. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO2 could be related to a larger dielectric constant of the high-k layer.

The strain in Si, on which single-crystalline CeO2 gate oxide was epitaxially grown, was investigated by evaluating lattice spacings in CeO2 and Si precisely. It is found that the lattice spacings in epitaxial CeO2 isotropically expanded by similar to1%, compared with those in bulk polycrystalline CeO2. The oxygen-defect-induced state was observed in the CeO2 valence band edge. The decrease of Coulomb interaction in ionic oxide due to the oxygen defects may induce the expansion of the lattice spacings in CeO2. It is clarified that Si at 50 nm depth from the CeO2/Si interface was tensile strained owing to the expansion of the lattice spacings in CeO2.

We have investigated the reason behind the enhancement of dielectric constant (ε), which occurred in CeO2 directly grown on Si(111). ε of directly grown CeO2 is enhanced to 52, which is twice as large as the reported value. From in-plane X-ray diffraction measurements and electron diffraction pattern observations using a transmission electron microscope, it has been found that the lattice spacings in CeO2 were isotopically expanded by 0.6%, as compared with the reported values in bulk CeO2. In addition, from X-ray photoelectron spectroscopy measurements, the existence of oxygen defects in CeO2 was confirmed. The oxygen defects in CeO2 may cause the decrease in coulomb interaction in the ionic crystal, resulting in the expansion of lattice spacings. The enhancement of ion movability, due to the expansion of lattice spacings is considered as the reason behind the enhancement of ε.

We investigate an origin of the Fermi-level pinning at the gate electrode/HfO/sub x/(N) interface, and propose a new technology for tuning the work function with a partial silicidation of Pt on HfO/sub x/ (N). It is clearly shown that the effective work functions (/spl Phi/ /sub m,eff/) of fully silicided (FUSI) NiSi and PtSi on HfO/sub x/(N) are rigidly fixed due to the Fermi-level pinning, and that the impurity doping does not help changing /spl Phi/ /sub m,eff/ at all. The large flatband voltage (VFB) shifts of FUSI PtSi MOSFETs have been observed irrespective of Si deposition processes. On the basis of these new findings, nMOSFET with pinned n+poly-Si and pMOSFET with partially pinned PtSi on HfO/sub x/ (N) for a balanced CMOS have been proposed, and both of them have shown good electrical properties. Furthermore, it is experimentally discussed that the control of the Si atom content at the PtSi/sub x//HfO/sub 2/ interface is a key factor to relax the pinning effect. The partial silicidation technology will be a most feasible method for advanced metal gate CMOS.

Energy-band diagrams and carrier-conduction mechanisms in ZrO/sub 2/ dielectrics were investigated by using X-ray photoemission spectroscopy and carrier separation measurements for ZrO/sub 2/ /Zr-silicate/Si structures. It was found that the carrier conduction mechanisms in ZrO/sub 2/ layer dominate the leakage current in the ZrO/sub 2/ /Zr-silicate/Si-stacked structure. Furthermore, it was found that the dominant electron conduction mechanism in ZrO/sub 2/ dielectrics is a Poole-Frenkel (P-F) conduction and that the dominant hole conduction mechanism in ZrO/sub 2/ dielectrics is a Fowler-Nordheim conduction. On the basis of the understanding of these carrier conduction mechanisms, it was indicated that the leakage current density in the dielectrics with the P-F conduction mechanism having the small barrier height of 0.8 eV could not be reduced below 1 A/cm/sup 2/ at the operation voltage of 1 V. Furthermore, we suggest that the ultrathin Zr-silicate single layer is a promising candidate gate dielectric material for advanced MISFET having 1-nm effective thickness.

In this paper, time evolutions of threshold voltage (V-TH) in p-MOSFETs have been investigated and discussed from the viewpoint of a statistical distribution. No change in the dispersion of the V-TH distribution under bias temperature (BT) stress was observed, whereas average values of V-TH monotonically increased. On the other hand, the V-TH distribution was remarkably deteriorated after soft breakdown progression of gate oxides.

We present a novel physical random number generator (RNG) that uses a metal-oxide semiconductor (MOS) capacitor after soft breakdown (SBD) as a random source. It is known that the electrical properties of MOS capacitors after SBD show large fluctuation. When the resistor in an astable multivibrator is replaced with an MOS capacitor after SBD, the multivibrator converts the noise signal into a rectangular wave whose period fluctuates randomly. A 1-bit counter and a flip-flop are used to generate random numbers from the fluctuating rectangular wave. Some high-level tests indicate that the generated random numbers have excellent quality for cryptographic applications. Even though our circuit is small and can be constructed using about 20 complementary-MOS logic gates and several passive devices, high-quality random numbers such as those generated by large physical RNGs can be obtained.

The breakdown characteristics of the gate insulator of nMOSFETs during transmission line pulsing for electrostatic discharge testing is evaluated by using device simulations. Experimental data for the gate bias and gate oxide thickness dependences of the number of pulses to breakdown are reproduced by adopting the anode-hole-injection model. The polarity of the gate bias dependence of the breakdown characteristics can be explained by the depletion of the gate electrode.

The role of oxygen inside deposited silicon oxynitride (SiON) films with respect to leakage current was investigated. We controlled the composition of bulk SiON film in accordance with the alloy model (Si3N4)x(SiO2)1−x regarding the ultrathin composite SiON structure and stacked SiON/SiO2 structure and measured electrical properties of these SiON films. Furthermore, we studied the conduction mechanisms of the leakage current for these films by using a direct tunneling (DT) current simulation with Wentzel–Kramers–Brillouin approximation, taking the dielectric constant, band profile, and effective mass into consideration. From these experiments and simulations, it was found that the leakage current of composite structure is lower than that of the stacked structure, even if those structures have the same alloy ratio x. Furthermore, we found the optimum film composition to minimize the DT current. The optimum structure was determined by the balance between the decrease in the electron DT current and the increase in the hole DT current due to the physical thickness and the valence-band barrier height.