The H2M (Hybrid-to-Monolithic) is a monolithic pixel sensor manufactured in a modified 65 nm CMOS imaging process with a small collection electrode. Its design addresses the challenges of porting an existing hybrid pixel detector architecture into a monolithic chip, using a digital-on-top design methodology, and developing a compact digital cell library. Each square pixel integrates an analog front-end and digital pulse processing with an 8-bit counter within a 35 mu m pitch. This contribution presents the performance of H2M based on laboratory and test beam measurements, including a comparison with analog front-end simulations in terms of gain and noise. A particular emphasis is placed on backside thinning in order to reduce material budget, down to a total chip thickness of 21 mu m for which no degradation in MIP detection performance is observed. For all investigated samples, a MIP detection efficiency above 99% is achieved below a threshold of approximately 205 electrons. At this threshold, the fake-hit rate corresponds to a matrix occupancy of fewer than one pixel per the 500 ns frame. Measurements reveal a non-uniform in-pixel response, attributed to the formation of local potential wells in regions with low electric field. A simulation flow combining technology computer-aided design, Monte Carlo, and circuit simulations is used to investigate and describe this behavior, and is applied to develop mitigation strategies for future chip submissions with similar features.

Conventional silicon photomultipliers (SiPMs) are well established as light detectors with single-photon-detection capability and used throughout high energy physics, medical, and commercial applications. The possibility to produce single photon avalanche diodes (SPADs) in commercial CMOS processes creates the opportunity to combine a matrix of SPADs and an application-specific integrated circuit in the same die. The potential of such digital SiPMs (dSiPMs) is still being explored, while it already is an established technology in certain applications, like light detection and ranging (LiDAR). A prototype dSiPM, produced in the LFoundry 150-nm CMOS technology, was designed and tested at DESY. The dSiPM central part is a matrix of 32 by 32 pixels. Each pixel contains four SPADs, a digital front-end, and has an area of 69.6 x 76 mu m2. The chip has four time-to-digital converters and includes further circuitry for data serialization and data links. This work focuses on the characterization of the prototype in an electron beam at the DESY II Test Beam facility, to study its capability as a tracking and timing detector for minimum ionizing particles (MIPs). The MIP detection efficiency is found to be dominated by the fill factor and on the order of 31%. The position of the impinging MIPs can be measured with a precision of about 20 mu m, and the time of the interaction can be measured with a precision better than 50 ps for about 85 % of the detected events. In addition, laboratory studies on the breakdown voltage, dark count rate, and crosstalk probability, as well as the experimental methods required for the characterization of such a sensor type in a particle beam are presented.

CERN's strategic R&D programme on technologies for future experiments recently started investigating the TPSCo 65nm ISC CMOS imaging process for monolithic active pixels sensors for application in high energy physics. In collaboration with the ALICE experiment and other institutes, several prototypes demonstrated excellent performance, qualifying the technology. The Hybrid-to-Monolithic (H2M), a new test-chip produced in the same process but with a larger pixel pitch than previous prototypes, exhibits an unexpected asymmetric efficiency pattern. This contribution describes a simulation procedure combining TCAD, Monte Carlo and circuit simulations to model and understand this effect. It proved able to reproduce measurement results and attribute the asymmetric efficiency drop to a slow charge collection due to low amplitude potential wells created by the circuit layout and impacting efficiency via ballistic deficit.

The high energy physics community recently gained access to the TPSCo 65 nm ISC (Image Sensor CMOS), which enables a higher in-pixel logic density in monolithic active pixel sensors (MAPS) compared to processes with larger feature sizes. To explore this novel technology, the Hybrid-to-Monolithic (H2M) test chip has been designed and manufactured. The design follows a digital-on-top design workflow and ports a hybrid pixel-detector architecture, with digital pulse processing in each pixel, into a monolithic chip. The chip matrix consists of 64×16 square pixels with a size of 35×35 μm 2 , and a total active area of approximately 1.25 mm 2 . The chip is operated and read out using the Caribou DAQ system. The measured threshold dispersion and noise agree with the expectation from front-end simulations. However, a non-uniform in-pixel response related to the size and location of the n-wells in the analog circuitry has been observed in test beam measurements and will be discussed in this contribution. This asymmetry in the pixel response, enhanced by the 35 μm pixel pitch — larger than in other prototypes — and certain features of the readout circuit, has not been observed in prototypes with smaller pixel pitches in this technology.

Caribou is a versatile data acquisition system used in multiple collaborative frameworks (CERN EP R D, DRD3, AIDAinnova, Tangerine) for laboratory and test-beam qualification of novel silicon pixel detector prototypes. The system is built around a common hardware, firmware and software stack shared accross different projects, thereby drastically reducing the development effort and cost. It consists of a custom Control and Readout (CaR) board and a commercial Xilinx Zynq System-on-Chip (SoC) platform. The SoC platform runs a full Yocto distribution integrating the custom software framework (Peary) and a custom FPGA firmware built within a common firmware infrastructure (Boreal). The CaR board provides a hardware environment featuring various services such as powering, slow-control, and high-speed data links for the target detector prototype. Boreal and Peary, in turn, offer firmware and software architectures that enable seamless integration of control and readout for new devices. While the first version of the system used a SoC platform based on the ZC706 evaluation board, migration to a Zynq UltraScale+ architecture is progressing towards the support of the ZCU102 board and the ultimate objective of integrating the SoC functionality directly into the CaR board, eliminating the need for separate evaluation boards. This paper describes the Caribou system, focusing on the latest project developments and showcasing progress and future plans across its hardware, firmware, and software components.

The DESY digital silicon photomultiplier (dSiPM) is a monolithic detector based on complementary metal-oxide-semiconductor (CMOS) single-photon avalanche diodes (SPADs) and features a fully digital readout. The dSiPM prototype was characterized using a picosecond injection laser. Different contributions to the time resolution from both SPADs and digitization electronics are quantified. The dSiPM achieves a temporal resolution of approximately 50 ps under optimal conditions, while localized charge deposition with the laser revealed in-pixel variations of the time resolution linked to the SPAD layout. Combining fast timing with a pixelated readout, the device is a promising candidate for 4D-tracking detectors and other precision timing applications.

Monolithic active pixel sensors (MAPS) are promising candidates for the next generation of vertex detectors at future lepton colliders. One particularly interesting advancement is the recently accessible 65 nm CMOS imaging technology, which offers higher logic density compared to larger feature-size processes, making it highly appealing to the High Energy Physics community. This paper highlights the progress made with prototypes, an analog test structure, DESY ER1, featuring a 2 x 2 active pixel configuration. The chip is integrated into the Caribou DAQ system, and detailed laboratory and test beam characterizations have been conducted. The DESY ER1 provides access to analog waveforms generated by the charge-sensitive amplifier with a Krummenacher feedback loop. The paper presents the initial testing results of DESY ER1 at sensor bias voltage of-3.6 V, including the charge calibration with Fe-55 and tracking performance characterization in test beam. The test beam measurements shows that the time resolution for detecting charged particles is below 8.72 ns at a threshold of 200 e-.

This contribution describes a monolithic digital silicon photomultiplier (dSiPM), designed and characterized at DESY. It consists of an array of single photon avalanche diodes (SPADs) arranged in a 32 x 32-pixel matrix at 70 μm pitch, with embedded CMOS circuitry for on-chip signal processing. The dSiPM is designed in LFoundry’s 150-nm CMOS process employing a fully characterized SPAD design provided by the manufacturer. It enables in-pixel sensor-signal digitization and masking, and provides the full hit map and time stamping at 3-MHz frame rate with a resolution better than 100 ps. Especially the availability of highly granular position information will be beneficial for applications like the readout of scintillating fibers, or the detection of minimum-ionizing particles (MIPs). Several measurements were carried out in the laboratory and at the DESY II test-beam facility using the Caribou readout system. The dark-count rate as function of the overvoltage and temperature, the TDC resolution, as well as their differential and integral nonlinearity are presented. The dSiPM was used to identify MIPs in the test beam and has demonstrated a detection efficiency of 30 %, limited by the fill factor. Comparing the time measurements of two dSiPMs installed at the test beam, show a time resolution on the order of 50 ps.

A Large Ion Collider Experiment (ALICE) has been conceived and constructed as a heavy-ion experiment at the LHC. During LHC Runs 1 and 2, it has produced a wide range of physics results using all collision systems available at the LHC. In order to best exploit new physics opportunities opening up with the upgraded LHC and new detector technologies, the experiment has undergone a major upgrade during the LHC Long Shutdown 2 (2019–2022). This comprises the move to continuous readout, the complete overhaul of core detectors, as well as a new online event processing farm with a redesigned online-offline software framework. These improvements will allow to record Pb-Pb collisions at rates up to 50 kHz, while ensuring sensitivity for signals without a triggerable signature.

Analogue test structures were fabricated using the Tower Partners Semiconductor Co. CMOS 65 nm ISC process. The purpose was to characterize and qualify this process and to optimize the sensor for the next generation of Monolithic Active Pixels Sensors for high-energy physics. The technology was explored in several variants which differed by: doping levels, pixel geometries and pixel pitches (10-25 mu m). These variants have been tested following exposure to varying levels of irradiation up to 3 MGy and 10(16) 1 MeV n(eq) cm(-2). Here the results from prototypes that feature direct analogue output of a 4 x 4 pixel matrix are reported, allowing the systematic and detailed study of charge collection properties. Measurements were taken both using Fe-55 X-ray sources and in beam tests using minimum ionizing particles. The results not only demonstrate the feasibility of using this technology for particle detection but also serve as a reference for future applications and optimizations.

Silicon Photomultipliers (SiPMs) are the state-of-the-art technology in single-photon detection with solid-state detectors. Single Photon Avalanche Diodes (SPADs), the key element of SiPMs, can now be manufactured in CMOS processes, facilitating the integration of a SPAD array into custom monolithic ASICs. This allows implementing features such as signal digitization, masking, full hit-map readout, noise suppression, and photon counting in a monolithic CMOS chip. The complexity of the off-chip readout chain is thereby reduced. These new features allow new applications for digital SiPMs, such as 4D-tracking of charged particles, where spatial resolutions of the order of 10 mu m and timestamping with time resolutions of a few tens of ps are required. A prototype of a digital SiPM was designed at DESY using the LFoundry 150 nm CMOS technology. Various studies were carried out in the laboratory and at the DESY II test-beam facility to evaluate the sensor performance in Minimum Ionizing Particles (MIPs) detection. The direct detection of charged particles was investigated for bare prototypes and assemblies coupling dSiPMs and thin LYSO crystals. Spatial resolution similar to 20 mu m and a full-system time resolution of similar to 50 ps are measured using bare dSiPMs indirect MIP detection. Efficiency >99.5 %, low noise rate and time resolution <1 ns can be reached with the thin radiator coupling.

This paper presents the design and characterization of a monolithic integrated circuit (IC) including digital silicon photomultipliers (dSiPMs) arranged in a 32$~\times~$32 pixel matrix at 70$~\mu$m pitch. The IC provides per-quadrant time stamping and hit-map readout, and is fabricated in a standard 150-nm CMOS technology. Each dSiPM pixel consists of four single-photon avalanche diodes (SPADs) sharing a quenching and subsequent processing circuitry and has a fill factor of 30$~\%$. A sub-100$~$ps precision, 12-bit time-to-digital converter (TDC) provides timestamps per quadrant with an acquisition rate of 3$~$MHz. Together with the hit map, the total sustained data throughput of the IC amounts to 4$~$Gbps. Measurements obtained in a dark, temperature-stable environment as well as by using a pulsed laser environment show the full dSiPM-IC functionality. The dark-count rate (DCR) as function of the overvoltage and temperature, the TDC resolution, differential and integral nonlinearity (DNL/INL) as well as the propagation-delay variations across the matrix are presented. With aid of additional peripheral test structures, the main building blocks are characterized and key parameters are presented.

Silicon Photomultipliers (SiPMs) are state-of-the-art photon detectors used in particle physics, medical imaging, and beyond. They are sensitive to individual photons in the optical wavelength regime and achieve time resolutions of a few tens of picoseconds, which makes them interesting candidates for timing detectors in tracking systems for particle physics experiments. The Geiger discharges triggered in the sensitive elements of a SiPM, Single-Photon Avalanche Diodes (SPADs), yield signal amplitudes independent of the energy deposited by a photon or ionizing particle. This intrinsically digital nature of the signal motivates its digitization already on SPAD level.A digital SiPM (dSiPM) was designed at Deutsches Elektronen Synchrotron (DESY), combining a SPAD array with embedded CMOS circuitry for on-chip signal processing. A key feature of the DESY dSiPM is its capability to provide hit-position information on pixel level, and one hit time stamp per quadrant at a 3MHz readout-frame rate. The pixels comprise four SPADs and have a pitch of about 70μm. The four time stamps are provided by 12bit Time-to-Digital Converters (TDCs) with a resolution better than 100ps.The chip was characterized in the laboratory to determine dark count rate, breakdown voltage, and TDC characteristics. Test-beam measurements are analyzed to assess the DESY dSiPMs performance in the context of a 4D-tracking applications. The results demonstrate a spatial hit resolution on a pixel level, a minimum-ionizing particle detection efficiency of about 30% and a time resolution in the order of 50ps.

A novel approach for designing the next generation of vertex detectors foresees to employ wafer-scale sensors that can be bent to truly cylindrical geometries after thinning them to thicknesses of 20-40$\mu$m. To solidify this concept, the feasibility of operating bent MAPS was demonstrated using 1.5$\times$3cm ALPIDE chips. Already with their thickness of 50$\mu$m, they can be successfully bent to radii of about 2cm without any signs of mechanical or electrical damage. During a subsequent characterisation using a 5.4GeV electron beam, it was further confirmed that they preserve their full electrical functionality as well as particle detection performance. In this article, the bending procedure and the setup used for characterisation are detailed. Furthermore, the analysis of the beam test, including the measurement of the detection efficiency as a function of beam position and local inclination angle, is discussed. The results show that the sensors maintain their excellent performance after bending to radii of 2cm, with detection efficiencies above 99.9% at typical operating conditions, paving the way towards a new class of detectors with unprecedented low material budget and ideal geometrical properties.

An ever-increasing demand for high-performance silicon sensors requires complex sensor designs that are challenging to simulate and model. The combination of electrostatic finite element simulations with a transient Monte Carlo approach provides simultaneous access to precise sensor modelling and high statistics. The high simulation statistics enable the inclusion of Landau fluctuations and production of secondary particles, which offers a realistic simulation scenario. The transient simulation approach is an important tool to achieve an accurate time-resolved description of the sensor, which is crucial in the face of novel detector prototypes with increasingly precise timing capabilities. The simulated time resolution as a function of operating parameters as well as the full transient pulse can be monitored and assessed, which offers a new perspective on the optimisation and characterisation of silicon sensors. In this paper, a combination of electrostatic finite-element simulations using 3D TCAD and transient Monte Carlo simulations with the Allpix Squared framework are presented for a monolithic CMOS pixel sensor with a small collection diode, that is characterised by a highly inhomogeneous, complex electric field. The results are compared to transient 3D TCAD simulations that offer a precise simulation of the transient behaviour but long computation times. Additionally, the simulations are benchmarked against test-beam data and good agreement is found for the performance parameters over a wide range of different operation conditions.

Small collection-electrode monolithic CMOS sensors profit from a high signal-to-noise ratio and a small power consumption, but have a limited active sensor volume due to the fabrication process based on thin high-resistivity epitaxial layers. In this paper, the active sensor depth is investigated in the monolithic small collection-electrode technology demonstrator CLICTD. Charged particle beams are used to study the charge-collection properties and the performance of devices with different thicknesses both for perpendicular and inclined particle incidence. In CMOS sensors with a high-resistivity Czochralski substrate, the depth of the sensitive volume is found to increase by a factor two in comparison with standard epitaxial material and leads to significant improvements in the hit-detection efficiency and the spatial and time resolution.

The CLIC Tracker Detector (CLICTD) is a monolithic pixel sensor. It is fabricated in a 180 nm CMOS imaging process, modified with an additional deep low-dose n-type implant to obtain full lateral depletion. The sensor features a small collection diode, which is essential for achieving a low input capacitance. The CLICTD sensor was designed as a technology demonstrator in the context of the tracking detector studies for the Compact Linear Collider (CLIC). Its design characteristics are of broad interest beyond CLIC, for HL-LHC tracking detector upgrades. It is produced in two different pixel flavours: one with a continuous deep n-type implant, and one with a segmented n-type implant to ensure fast charge collection. The pixel matrix consists of 16 x 128 detection channels measuring 300 mu m x 30 mu m. Each detection channel is segmented into eight sub-pixels to reduce the amount of digital circuity while maintaining a small collection electrode pitch. This paper presents the characterisation results of the CLICTD sensor in a particle beam. The different pixel flavours are compared in detail by using the simultaneous time-over-threshold and time-of-arrival measurement functionalities. Most notably, a spatial resolution down to (4.6 +/- 0.2) mu m is measured. A time resolution down to (5.8 +/- 0.1) ns is observed, after applying an offline time-walk correction using the pixel-charge information. The hit detection efficiency is found to be well above 99.7 % for thresholds of the order of several hundred electrons.

Corryvreckan is a versatile, highly configurable software with a modular structure designed to reconstruct and analyse test beam and laboratory data. It caters to the needs of the test beam community by providing a flexible offline event building facility to combine detectors with different readout schemes, with or without trigger information, and includes the possibility to correlate data from multiple devices based on timestamps. Hit timing information, available with high precision from an increasing number of detectors, can be used in clustering and tracking to reduce combinatorics. Several algorithms, including an implementation of Millepede-II, are provided for offline alignment. A graphical user interface enables direct monitoring of the reconstruction progress and can be employed for quasi-online monitoring during data taking. This work introduces the Corryvreckan framework architecture and user interface, and provides a detailed overview of the event building algorithm. The reconstruction and analysis capabilities are demonstrated with data recorded at the DESY II Test Beam Facility using the EUDAQ2 data acquisition framework with an EUDET-type beam telescope, a Timepix3 timing reference, a fine-pitch planar silicon sensor with CLICpix2 readout and the AIDA Trigger Logic Unit. The individual steps of the reconstruction chain are presented in detail.

A novel monolithic pixelated sensor and readout chip, the compact linear collider tracker detector (CLICTD) chip, is presented. The CLICTD chip was designed targeting the requirements of the silicon tracker development for the experiment at the compact linear collider (CLIC) and has been fabricated in a modified 180 nm CMOS imaging process with charge collection on a high-resistivity p-type epitaxial layer. The chip features a matrix of $16\times 128$ elongated channels, each measuring $300\times 30\,\,\mu \text {m}^{2}$ . Each channel contains 8 equidistant collection electrodes and analog readout circuits to ensure prompt signal formation. A simultaneous 8-bit time-of-arrival (with 10 ns time bins) and 5-bit time-over-threshold measurement is performed on the combined digital output of the 8 subpixels in every channel. The chip has been fabricated in two process variants and characterized in laboratory measurements using electrical test pulses and radiation sources. Results show a minimum threshold between 135 and 180 e − and a noise of about 14 e − rms. The design aspects and characterization results of the CLICTD chip are presented.

Caribou is a flexible data acquisition system for prototyping silicon pixel detectors. The core of the system consists of the Control and Readout (CaR) board, a versatile module providing the hardware environment for various target ASICs, including powering and slow-control infrastructure, and high-speed full-duplex GTX links up to 12.5 Gbps. The CaR board connects to a Zynq system-on-chip board which runs a fully-featured Yocto-based Linux distribution (Poky) and a data acquisition software (Peary). Using the Caribou system significantly reduces the time required to test and debug detector prototypes by providing ready-to-use peripheries and their software interfaces together with a widely adjustable data acquisition framework that is suitable for a variety of detectors. The paper describes the hardware and software architecture of the system, its capabilities, and examples of projects where it has been used.