This paper presents an amplifier with low noise, high gain, low power consumption, and high linearity for electrocardiogram (ECG) recording. The core of this design is a chopper-stabilized capacitive-feedback operational transconductance amplifier (OTA). The proposed OTA has a two-stage structure, with the first stage using a combination of current reuse and cascode techniques to obtain a large gain at low power and the second stage operating in Class A state for better linearity. The amplifier additionally uses a DC servo loop (DSL) to improve the rejection of DC offsets. The amplifier is implemented in a standard 0.13 μm CMOS process, consuming 1.647 μA current from the supply voltage of 1.5 V and occupying an area of 0.97 mm2. The amplifier has a 0.5 Hz to 6.1 kHz bandwidth and 59.7 dB gain while having no less than a 65 dB common-mode rejection ratio (CMRR). The amplifier’s total harmonic distortion (THD) is less than 0.1% at 800 mVpp output. The amplifier can provide a noise level of 1.18 μVrms in the 0.5 Hz to 500 Hz bandwidth that the ECG signal is interested in and has 3.38 μVrms input-referred noise (IRN) over the entire bandwidth, so its noise efficiency factor (NEF) is 2.13.

This paper introduces a new high-performance successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-speed and low-power wireless local area network (WLAN) applications using a SMIC 55 nm 1p8m CMOS process. The design employs several innovative techniques, including an improved bootstrap switch with high linearity, a 4-reference voltage method to minimize capacitive digital-to-analog converter (CDAC) mismatch, a kickback-canceling comparator to eliminate kick-back noise, and redundant design-assisted window-opening SAR logic to decrease conversion time. Experimental results reveal that the proposed ADC achieves an impressive signal-to-noise and distortion ratio (SNDR) of 55.3 dB and a spurious-free dynamic range (SFDR) of 66.6 dB at a sampling rate of 200 MHz with Nyquist frequency input while consuming a power of 2.8 mW at a 1.2 V power supply. This corresponds to a figure-of-merit (FoM) value of 29 fJ/conversion-step. Thanks to the incorporation of the 4-reference voltage method, the ADC demonstrates a significant area advantage compared to other designs with similar FOM values utilizing more advanced processes, occupying a mere 0.008 mm(2) of core area.

A 3.3 V mode-switching RF CMOS power amplifier (PA) for WLAN applications is presented, which is integrated into a 55-nm bulk CMOS process. The proposed PA offers both static control and dynamic power control, allowing it to operate efficiently in both low-power and high-power modes. The pure low-power mode is achieved by reducing power cells, which are also used for linearization in high power mode. The low-power mode is achieved by reducing the number of power cells which are also used for linearization in the high-power mode. In the dynamic power control mode, the total AM–AM and AM–PM distortion is effectively compensated for by dynamically controlling the number of power cells and adjusting the matching input. The proposed PA achieves an output P1dB of 27.6 dBm with a PAE of 32.7% and an output P1dB of 17.7 dBm with a PAE of 10% in high-power and low-power modes, respectively. It is measured with an 802.11 n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 19 dBm under an error-vector-magnitude (EVM) of −27 dB.

In this paper, a dual-mode step-down DC-DC converter with an automatic mode-switching circuit is implemented in a 28 nm digital CMOS process and embedded in an RF transceiver chip to power the digital part. The proposed automatic mode-switching circuit includes a frequency-voltage conversion circuit that is designed according to the principle of charge redistribution on capacitance. The converter can switch modes according to the load without external intervention. This converter, along with a PMU sequencer, can also provide a solution for low-power design for system-on-chip applications. The IC occupies a total die area of 0.378 mm(2). The input voltage of the converter is 3.3 V, the output voltage is 1.05 V, and the maximum load current can reach 1 A. The converter shows a conversion efficiency of not less than 81% at a full load range and can achieve a peak conversion efficiency of 91% when the load current is 100 mA. The load range of the PWM mode is 1 A to 50 mA, and that of the PFM mode is 100 mA to 1 mA. The combination of zero-crossing detection circuitry and freewheel switches can reduce energy loss and eliminate additional electromagnetic interference.

AbstractAn optical receiver front-end circuit is designed for passive optical network and fabricated in a 0.18 um CMOS technology. The whole circuit consists of a transimpedance amplifier (TIA), a single-ended to differential amplifier and an output driver. The TIA employs a cascode stage as the input stage and auxiliary amplifier to reduce the miller effect. Current injecting technique is employed to enlarge the input transistor’s transconductance, optimize the noise performance and overcome the lack of voltage headroom. To achieve a wide dynamic range, an automatic gain control circuit with self-adaptive function is proposed. Experiment results show an optical sensitivity of –28 dBm for a bit error rate of 10

A burst-mode laser diode driver (LDD) with dual-loop power control circuit was designed for the passive optical network (PON) applications. The charge compensation and dynamic bias circuit was employed to reduce the rising and falling time of the output current and enlarge the output current capability. A dual-loop power control feedback circuit was proposed to avoid the variations of average power and the extinction ratio with temperature. The proposed laser diode driver was implemented in a 0.18μm RF CMOS technology and the chip area was 1600μm ×800μm. Experiment results show that the output bias current and the modulating current can reach 90 mA. The burst-on time of the LDD is less than 2 ns and the burst-off time is less than 1 ns with 2.5 Gbit/s data transmitting rate and 41 ps magnitude. The average power stability and the extinction ratio stability of the LDD is ±0.26 dB and ±1 dB, respectively. The proposed LDD meets the needs of the optical power and stability of the laser for PONs.

An inductorless 2.5 Gbit/s preamplifier was designed for the application of optical receivers in passive optical network and fabricated in a 0.18 μm RF CMOS process.The preamplifer consisted of a transimpedance amplifier,a single-ended Ti differential ended amplifier and an output driver.The transimpedance amplifier was based on a three-stage push-pull inverter structure.The special configuration allows for high gain and low noise performance.Phantom zeros technique was analyzed and employed to improve the bandwidth and ensure the stability of the TIA.To achieve a wide dynamic range,an automatic gain control technique with self-adaptive function was proposed to keep the bandwidth constant and stabilize the feedback network.The results show that the optical sensitivity is-29 dB·m and the maximum input optical power is 2 dB.m for 2.5 Gbit/s operation with a bit error rate of 10-10.The dynamic range is 31 dB·m.The chip consumes about 30 mW from a single 1.8 V supply.The chip area is 1 × 0.7 mm2.

基于5.8 GHz电子不停车收费系统（electronic toll collection,ETC）应用,介绍了射频收发芯片中唤醒接收机（wake-up receiver,WuR）的模拟前端电路。采用了一种共源共栅结构的射频包络检波器（RF envelop detector,RFED）并分析了其频率转换机制,利用亚阈值偏置技术,实现了高电流效率和高频率转移效率。设计了具有带通滤波特性的可编程增益放大器（PGA）、带迟滞功能的比较器以及电流基准源等子电路。电路基于TSMC 0.18μm CMOS工艺制造,占用芯片面积约为430μm×300μm。实测结果表明,在3.3 V电源供电条件下,模拟前端电路仅消耗2.5μA电流,实现了-45 dBm的唤醒接收灵敏度,满足ETC WuR的设计指标和实际应用需求。

A new BGR circuit with high PSRR and low TC is proposed.The PSRR performance of BGR is discussed in detail,especially at high frequency.Then,a high PSRR over a wide frequency range is achieved.The circuit is fabricated in 0.35 μm BiCMOS process.Simulation results show that the PSRR is-108.5 dB at 1 Hz,and-58.9 dB at 15 MHz.A second order curvature compensated circuit is designed.The temperature coefficient is as low as 1.5 ppm/℃ over a temperature range-40 ℃ to 95 ℃.

A novel auto-squelch circuit in transimpedance amplifier for optical fiber communication was designed and realized in a standard 0.35 μm CMOS technology.The system architecture described in this paper is composed of a received signal strength detector,a comparing reference generator,a hysteresis comparator and a squelch control cell.When input current signal is below the squelch assert level,the squelch circuit will disable the data path automatically.Otherwise,when input current signal is above the squelch de-assert level,the squelch circuit will open the data path.The squelch circuit was implemented in 155 Mb / s tran simpedance amplifier with-40 dBm sensitivity(BER = 10-10).The squelch assert and de-assert level are 47 nA and 85 nA respectively.And the squelch hysteresis width is 2.57 dB.

This letter presents a current-shaping technique for static MOS current-mode logic (MCML) prescalers. Simply with two extra current-shaping capacitors the self-oscillating frequecy is increased. A current vector model is also presented to illustrate the principles. The prescaler with the current-shaping technique was fabricated in a 0.18μm CMOS technology with a reference classic one. The measurement results show that the self-oscillating frequency of the prescaler with current-shaping achieves an improvement of 10%, resulting a 6 GHz highest operating frequency while the classic one could only work at 5.3 GHz. Consequently, the current-shaping technique improves the maxim divide range of the prescaler with 13.2%.

To reduce the noise figure in the tradition low noise amplifier,extend the bandwidth and achieve more precise step accuracy,a RF programmable amplifier with low noise single-ended differential circuit is proposed.The single-ended differential circuit uses the noise cancellation method to reduce the noise figure and uses the capacitance cross technique to extend the bandwidth.The improved source-level follower structure can achieve more precise step accuracy.The circuit is fabricated in 0.18 mm CMOS process.Under 1.8 V power supply and 170-870 MHz frequency signal input,the circuit achieves a 3.8 dB noise figure.The circuit shows a 55 dB gain control range by 0.8 dB each step.The overall power consumption is less than 14.76 mW,and the die area is 800 m m ×600 m m.The test result shows that the circuit can provide lower noise figure and cover wider bandwidth while consumes the same current comparing with the tradition structure and the circuit can provide more precise step accuracy.

To solve the problem that the tuner bandwidth is wider, a digital programmable RF wideband amplifier for UV-band digital (DTV) tuner is proposed in this paper to achieve a lower noise figure and improve the linearity of the circuit. The noise canceling technology is introduced to reduce the noise figure. The linearity improvement techniques are introduced to improve the linearity of the intermediate circuit and the source-level follower structure is improved to achieve more precise step accuracy are introduced. The circuit is fabricated in 0.18 um CMOS process. Under 1.8 V power supply and 170~870 MHz frequency signal input, the circuit achieves a 3.8 dB noise figure. The circuit can provide -12 dBm third-order intercept points when the gain is set to maximum. The circuit shows a 55 dB gain control range by 0.8 dB each step. The overall power consumption is less than 14.76 mW, and the die area is 800 um*600 um. The testing result shows that the noise figure is reduced as compared with the circuit mentioned before, while extend the bandwidth to UV band, and the linearity is improved as well.

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented. The power solution involves a DC-DC buck converter and a followed low-dropout regulator (LDO). The pulsewidth-modulation (PWM) control method is adopted for better noise performance. An improved low-power highfrequency PWM control circuit is proposed, which halves the average quiescent current of the buck converter to 80 mu A by periodically shutting down the OTA. The size of the output stage has also been optimized to achieve high efficiency under a light load condition. In addition, a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current. Fabricated with commercial 180-nm CMOS technology, the DC-DC converter achieves a peak efficiency of 93.1% under a 2 MHz working frequency. The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.

An output amplitude configurable wideband automatic gain control (AGC) with high gain step accuracy for the GNSS receiver is presented. The amplitude of an AGC is configurable in order to cooperate with baseband chips to achieve interference suppression and be compatible with different full range ADCs. And what's more, the gain-boosting technology is introduced and the circuit is improved to increase the step accuracy. A zero, which is composed by the source feedback resistance and the source capacity, is introduced to compensate for the pole. The AGC is fabricated in a 0.18 μm CMOS process. The AGC shows a 62 dB gain control range by 1 dB each step with a gain error of less than 0.2 dB. The AGC provides 3 dB bandwidth larger than 80 MHz and the overall power consumption is less than 1.8 mA, and the die area is 800 × 300 μm2.

A wideband digitally controlled gain amplifier(DGA) with high accuracy was presented,in which gain-boosting technology was used to improve gain step accuracy.A zero composed of source feedback resistance and source capacitance was introduced to offset the pole.Fabricated in 0.18 μm CMOS process,the circuit occupied a chip area of 800 μm×300 μm.Test results showed that the DGA,which consumed less than 1.5 mA of power,had a gain control range of 62 dB by 1 dB step with a gain error less than 0.2 dB,and a 3 dB-bandwidth up to 80 MHz.

An analog/digital reconfigurable automatic gain control (AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What's more, a novel DC offset cancellation (DCOC) circuit with an HPCF (high pass cutoff frequency) less than 10 kHz is proposed. The AGC is fabricated by a 0.18 μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 × 300 μm2.

This paper presents a design of an Automatic Gain Control(AGC) for zero-IF receiver by utilizing a parallel compensation DC Offset Canceller which can effectively suppress DC Offset from the previous circuit and self-mismatch.It achieves better performance in DC Offset Cancellation and lower HPCF compared to conventional ones.And what's more,there is not stability problem existed in feedback configuration.The AGC is realized in 0.18 μm CMOS technology with 1.8 V power supply voltage providing a stable output signal of 700 mVp-p,a dynamic range of 50 dB and the 3 dB bandwidth of 60 MHz with a HPCF lower than 10 kHz.Moreover,the output DC Offset voltage is less than 5 mV while dissipating total current of 4.31 mA and area of 710 μm×110 μm.

>This paper presents a novel approach for designing a reconfigurable variable gain amplifier(VGA) for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V.The 3 dB bandwidth is about 80 MHz for all levels of control voltage(all gains).Also,the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input.The overall power consumption is less than 3 mA,and die area is 705×100μm 2 .