We propose a direct experimental extractiontechnique for trapped charges and quantitative energyband diagrams (EBDs) in the ferroelectric field-effecttransistors (FeFETs) with metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) structure, derived fromthe physical relationship betweenVthand gate-sideinterlayer (G.IL) thickness. By decoupling trapped chargesand ferroelectric polarization, we reveal that: 1) thegate-injected charges and channel-injected charges areexcessive and maintain consistent ratios to ferroelectricpolarization (similar to 157% and similar to 127%, respectively); 2) retentionloss (RL) originates from the de-trapping of gate-injectedcharges rather than ferroelectric depolarization; and 3) asthe G.IL thickens, the gate-injected charge de-trappingpath transforms from gate-side to channel-side. To addressthe RL, careful material design, optimization, and bandgapengineering in the MIFIS structure are crucial. This workadvances the understanding of high retention strategiesfor MIFIS-FeFETs in 3-D FE nand.

In this paper, the temperature dependence of parallel and overlapping MOS-SCR ESD protection structures fabricated by DSOI process is investigated. Transmission Line Pulse (TLP) experiments results indicate that as the ambient temperature increases from 25 degrees C to 185 degrees C the trigger and holding voltages of the overlapping structure decrease by 41.9 % and 35.7 %, respectively, while those of the parallel structure decrease by 35.7 % and 21.7 %. The overlapping structure exhibits stronger temperature sensitivity in triggering. To elucidate the underlying mechanisms, 3D TCAD simulations were developed to capture the temperature-dependent trends and enable physical mechanism analysis. The results reveal that enhanced electro-thermal coupling between the GGNMOS and SCR in the overlapping configuration can accelerate local temperature elevation, intensify the band-to-band tunneling (BTBT) effect, and thereby render the device more susceptible to triggering. The results elucidate the role of structural design in high-temperature electrostatic discharge behaviour, offering useful guidance for enhancing the reliability of DSOI ESD protection devices in high-temperature environments.

In this study, an oxygen atmosphere post-deposition annealing (O-2 PDA) method is proposed to enhance the performance of ferroelectric field-effect transistors (FeFETs) with the TiN/SiO2/Hf0.5Zr0.5 O-2/SiO2/Si gate structure. The O-2 treatment duration was varied, ranging from 0 s (without PDA) to 120 s, with 30 and 60 s as intermediate conditions, and the key findings are as follows: 1) the memory window (MW) first increases and then decreases as O-2 PDA duration increases. The maximum MW is achieved under 60 s O-2 PDA, which exhibits a 16% enhancement compared to the 0 s condition, attributed to the increased charge trapping at the SiO2/Hf0.5Zr0.5 O-2 interface; and 2) the O-2 PDA treatment improves endurance from 3 & times; 10(4) to 2 & times; 10(5 ) cycles, which is attributed to suppressing defect generation near the channel-side interface. The linear extrapolation suggests all devices with different O-2 PDA durations achieve a data retention of ten years. This study provides a viable strategy for advancing the development of MIFIS-FeFETs targeting 3-D VNAND applications.

Based on SOI Pseudo-MOS, an equivalent circuit model of non-equilibrium body potential (Vneq) is proposed. The non-equilibrium majority carriers cannot be neglected to interpret the mechanism of Vneq. An accurate mathematical Vneq is determined through bringing non-equilibrium majority carriers into the discrete Poisson equation, which is validated by TCAD simulations.

In recent years, DeepSeek has achieved strong inference performance but remains hard to deploy on energy-constrained edge devices. This paper presents the DeepSeek Processing Element (DSPE), an edge-oriented architecture that alleviates the model's heavy computational and energy demands. DSPE introduces three techniques: the MerkleTree-based Incremental Pruning Scheme (MIPS) for secure redundant-vector reduction, the Multi-Stage Boothing Lookup Method (MBLM) for bit-flip-aware approximate multiplication, and the Dynamic Adaptive Posit Processing Mechanism (DAPPM), which introduces a new DA-Posit format and its corresponding hardware multiplication architecture. Implemented in TSMC 28nm CMOS, DSPE achieves 109.4 TFLOPS/W energy efficiency compared with state-of-the-art designs and offers a scalable foundation for edge deployment.

This paper proposes 3D-MANN, a reconfigurable compute-in-memory (CIM) architecture for Memory-Augmented Neural Network (MANN) inference based on 3D NAND flash memory. The architecture addresses key limitations of prior MANN-oriented CIM solutions, including GPU dependency and limited flexibility. First, it exploits intrinsic post-programming threshold voltage broadening of 3D NAND cells to construct the random projection matrix for locality-sensitive hashing (LSH). Second, it reveals inherent consistency among MAC, LSH, and TCAM operations, enabling a multi-functional macro with unified dataflow and peripheral reuse for dynamic reconfiguration without re-tapeout. Third, a ternary feature prototype compression scheme reduces TCAM storage overhead. Fourth, based on 128-layer 3D NAND chip measurements, optimization strategies including pre-baking for LSH and redundant array compensation for MAC/TCAM mitigate threshold voltage drift. Evaluations show 94.1%/97.6% accuracy (5-way 1-shot/5-shot) on Omniglot, approaching software baselines, with energy efficiency of 28.12 TOPS/W and performance density of 0.337 TOPS/mm2.

In this letter, we present an epi-Si channel ferroelectric vertical gate-all-around (FEVGAA) FET featuring a gate and channel interlayer (G.IL/C.IL) co-design to achieve a wide memory window (MW) and robust reliability. The performance enhancement stems from two synergistic mechanisms: (1) gate-injected charges (Q(tG)) induced by the G.IL, and (2) C.IL nitridation, which raises trap formation energy while introducing positive fixed charges to improve endurance, retention, and read-disturb immunity. Enabled by this strategy, a record MW of 3.5 V is realized, representing a 7.7X expansion compared to the reference FE-only device. The maximum ISPE slope also improves 8.8X. Notably, the device endures 5 & times; 10(4) cycles with negligible Ion degradation at the large MW state. Endurance is further extended to 5 & times; 10(8) cycles with a nanosecond-level high operating speed. Moreover, the retention loss after 10 years is only 2.8%. In addition, the device exhibits strong immunity to read disturb for 106 cycles. This gate stack design expands the application of FEVGAA devices in high-density non-volatile memory.

This paper presents an LC oscillator integrated with a common-mode (CM) harmonic self-calibration system. The proposed design employs a harmonic resonance technique to suppress noise coupling and thereby improve phase noise (PN) performance. In addition, the self-calibration mechanism automatically aligns the CM resonance frequency to twice the fundamental frequency across the entire tuning range, enabling adaptive optimization of PN. The oscillator is designed in GF 22 nm FDSOI process and achieves a tuning range of 3.1-5.5 GHz with a power consumption of 5.7-11.7 mW. The simulation results show a PN of -129 to -129.8 dBc/Hz at a 1 MHz offset, corresponding to a figure-of-merit (FoM) of 188.2-196.1 dBc/Hz. These results confirm the effectiveness of the proposed self-calibrated CM resonance technique.

High-resolution short-wave infrared (SWIR) imaging requires photodetectors (PDs) with simultaneously low dark current and high responsivity. To achieve this goal, we demonstrate low-defect bulk germanium-on-insulator (bulk-GeOI) PDs designed for enhanced 1550 nm absorption and suppressed dark current via a resonant cavity and low-defect material platform. Devices were fabricated by direct bonding low-defect bulk Ge and thinning it to ~1300 nm, with an intrinsic layer thickness of only 800 nm. This design avoids epitaxial defects to lower intrinsic dark current while forming a resonant cavity for enhanced responsivity at 1550 nm. Precise doping and Al2O3/Si3N4 bilayer sidewall passivation were employed. From a design perspective, using low-defect bulk Ge minimizes the defects from epitaxial growth and reduces intrinsic dark current, while thinning the Ge layer enhances the resonant cavity effect to improve 1550 nm responsivity. Experimentally, despite the thin absorbing layer, our devices achieved nA-level dark currents (e.g., 18 nA at -1 V for 10 μm devices) alongside high responsivities. Detailed analysis indicates that this dark current is predominantly attributed to surface and sidewall defects from mesa etching, with minimal contribution from low-defect bulk material defects, validating the effectiveness of the bulk-Ge approach in suppressing intrinsic bulk leakage. Optically, the devices achieved high responsivities of 0.85 A/W (1310 nm) and 0.72 A/W (1550 nm), corresponding to external quantum efficiencies of 80.6% and 57.7%, respectively. This work establishes the bulk-GeOI platform as a promising path toward high-performance SWIR PDs, successfully decoupling high responsivity from bulk leakage and paving the way for future gains through refined surface and interface engineering.

We have presented PIN Ge-on-insulator (GOI) photodetectors (PDs) incorporating tensile-strained GeSi/Ge multiple quantum wells (MQWs) within the intrinsic layer. To control strain relaxation and reduce dark current, the thickness of the Ge spacer cap above the GeSi/Ge MQWs was systematically optimized. The optimized design yields a dark current density of 2.20 mA/cm2 and a responsivity of 1.01 A/W at 1550 nm, corresponding to a specific detectivity of 4.02 × 1010 cm·Hz1/2·W-1 under -1 V. The PDs exhibit enhanced responsivity at 1550 nm due to constructive optical interference within the SiO2 insulator layer. Moreover, the PD with a thicker spacer exhibits an extended cutoff wavelength of 1700nm, as confirmed by photoluminescence and spectral response measurements, which is attributed to the larger tensile strain in Ge-like Ge0.86Si0.14. These results demonstrate that GOI PDs with GeSi/Ge MQWs offer significant potential for high-performance, Ge-based extended short-wavelength infrared detection and imaging applications.

This study presents an effective strategy to reduce specific contact resistivity (ρc) of titanium-based Ohmic contacts through the incorporation of an ultrathin low-oxide-formation-enthalpy metal interlayer. Specifically, by introducing a 5-20 Å yttrium (Y) layer between titanium (Ti) and titanium nitride (TiN), the local distribution of oxygen impurities in the Ti/TiN stack is modulated, thereby further mitigating oxygen accumulation near the silicide/Si reaction region. This interfacial oxygen redistribution facilitates silicide formation and promotes the formation of the low-resistance C54-TiSi2 phase. Notably, the addition of a 10 Å Y interlayer yields a remarkable 35% reduction in ρc compared to conventional Ti-based contacts without a Y interlayer, achieving a value of 9.783×10-9 Ω·cm2.

This paper proposes a novel pre-treatment method using La(iPr2-FMD)3 (La-FMD), the La2O3 precursor in combination with annealing to mitigate the dipole-induced flat-band voltage (VFB) modulation effect. Specifically, after performing 3 cycles of La-FMD treatment on the interfacial layer (IL), high-kappa dielectric post-deposition annealing (PDA) and post-metallization annealing (PMA) at various temperatures were conducted, achieving a positive VFB modulation of 390 mV. Furthermore, La-FMD treatment significantly improves the Si/SiO2 interface quality and reduces the equivalent oxide thickness (EOT), while no degradation in EOT and interface state density (Dit) is observed after PMA at 400 degrees C-500 degrees C. In contrast, PDA and PMA at other temperatures lead to increased EOT and deteriorated Dit. Notably, EOT is reduced by approximately 1.3 & Aring; after La-FMD treatment compared to untreated samples, while the oxide trap density (Not) is reduced by 51.2%, and the interface state density (Dit) is reduced by 45.1%. The results demonstrate that the synergistic effect of La-FMD treatment and PMA annealing enables EOT scaling and interface quality improvement, while offering tunable flat-band voltage control through different annealing temperatures. This finding provides a new approach for precise flat-band voltage modulation in advanced nanosheet gate-all-around field-effect transistors (NS GAA-FETs). Post-metallization annealing achieves a positive VFB shift of up to 390 mV for threshold voltage modulation.La-FMD treatment enables equivalent oxide thickness (EOT) scaling of approximately 1.3 & Aring; without increasing physical thickness.Interface quality is improved, with interface state density (Dit) reduced by 51.2% and oxide trap density (Not) reduced by 45.8%.Annealing-induced La redistribution forms HfLaOx, weakening dipole strength and enabling tunable VFB control.

In this work, we realize a $950~^{\circ }$ C thermal budget of Al2O3-embedded Hf ${}_{{0}.{5}}$ Zr ${}_{{0}.{5}}$ O2 (HZO) ferroelectric in a polycrystalline silicon (Poly-Si) channel-last FeFET. This enhanced thermal stability is achieved by embedding Al2O3 dielectric layers into the HZO film. The Al2O3 layers separate ferroelectric grain boundaries and suppress leakage-path formation, and consequently improve the thermal stability of the ferroelectric HZO. By inserting two layers of 1-nm Al2O3 into HZO, the FeFET device shows the largest memory window of 5.69 V. This work confirms the feasibility of integrating HZO into 3-D nand technology and provides a method to further tune the memory characteristics of Ferro-nand.

In this work, we successfully fabricated p-channel optimized metallic source/drain Schottky barrier fully depleted silicon-on-insulator (O-MSD SB FDSOI) MOSFETs that perform comparably to or better than conventional raised source/drain (RSD) devices. Process optimization focused on hole Schottky barrier height (SBH) modulation in NiSi/n-Si Schottky junction diodes (SJDs) through silicide-induced dopant segregation (SIDS) and silicide-as-diffusion-source-induced dopant segregation (SADS). Dopant segregation (DS) forms a locally heavily doped "P+" region at the silicide/Si interface, thereby modulating the barrier profile to suppress off-state leakage and enhance on-state tunneling. In addition, we modified the SADS process to develop M-SADS and applied it to fabricate p-channel O-MSD SB MOSFETs, which exhibit effective gate-induced drain leakage (GIDL) suppression and achieve an on/off current (Ion/Ioff) ratio of 5.7×10⁸. These results demonstrate a process-level optimization for the studied FDSOI platform and indicate the potential for high-performance and low-power applications.

We propose a gate and channel interlayers (G.IL/C.IL) co-design scheme to improve the reliability of metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) FeFET. By implementing a thick high- $\boldsymbol{\kappa}$ AHA G.IL and a nitridated C.IL, we effectively suppress charge detrapping for retention and reduce the electric field in the G.IL (EG.IL) for endurance. We achieve an MIFIS with 3-bit operations under +14/-13V operating voltage (6 V memory window, $5 \times 10^{5}$ endurance cycles, and only 2.7% retention loss after 10 years). The devices also exhibit strong immunity to read disturb. Reliability tests under elevated temperatures also demonstrate excellent endurance, data retention, and read-disturb immunity. Furthermore, this scheme is verified on the FE vertical gate-all-around (VGAA) NAND cell $(\mathbf{L}_{\text{gate }}=\mathbf{6 0 n m}$) and also improves its reliability. This work presents a practical gate stack design for high reliability 3D FE NAND.

In this work, we fabricate FeFETs with a TiN/Al2O3/Hf0.5Zr0.5O2/Al2O3/Hf0.5Zr0.5O2/SiOx/Si (MAFAFOS) gate-stack, utilizing Al2O3 for both the tunneling dielectric layer (TDL) and gate interlayer (GIL). By using 2-nm TDL/3-nm GIL and reducing the unstable charges trapped at the GIL interface, we achieve a memory window (MW) of 9 V at an operating voltage of -13 +14 V and superior retention characteristics, with a 0.44% MW loss over 10 years. Quantification of the electric field across the TDL at V-g approximate to 0 V indicates that the TDL functions as an additional charge barrier and raises the energy band of the adjacent ferroelectric layer, leading to improved retention. This work demonstrates the potential of the MAFAFOS gate-stacks for high-performance 3-D Fe-NAND applications.

The synergistic effects of the total ionizing dose (TID) and single-event upset (SEU) are investigated in a 0.18-& micro;m double silicon-on-insulator (DSOI) static random access memory (SRAM), and the impacts of top silicon-layer thickness (T-SOI1) and back-gate bias are discussed. Experimental results show that the TID irradiation significantly enhances the SEU cross section; specifically, at LET = 86.1 MeV.cm(2)/mg, a TID of 1000 krad(Si) increases the SEU cross section by a factor of 2.7. Thanks to reduced charge collection, a 60.7% decrease in SEU cross section is observed under Ta-181(35+) irradiation when T-SOI1 is reduced from 65 to 45 nm. Moreover, a negative back-gate bias enhances the radiation hardness of the SRAM, achieving a 71% reduction in the SEU cross section under Ta-181(35+) ion exposure following a TID of 1000 krad(Si). Consequently, an optimized biasing scheme is proposed to balance the trade-offs between radiation hardness and key circuit performance metrics, including access time, area, and power consumption. The underlying physical mechanisms are further elucidated through TCAD and HSPICE simulations.

We demonstrate the first memtransistor-based gain-cell (MGC) compute-in-memory device implemented in a monolithic three-dimensional (M3D) chip integrating Si, IGZO, and CNTs technologies. Beyond logics, Si transistors employing dopantsegregation exhibit memtransistor characteristics suitable for memory applications. By vertically stacking an IGZO access transistor on the low-thermal-budget-Si (LT-Si) read memtransistor, an innovative hybrid 2T0C gain cell is realized, enabling low-voltage programmable multistate and stable CIM operation. The device is structurally matched with DEtection TRansformer (DETR) vision transformers, where persistent key-value (K/V) tensors of the frame are stored in memtransistors and dynamic object queries are parallelly pipelined into the storage nodes. Combined with CFET SRAM-DCIM and on-chip multiple spectral CNT-sensor, this end-to-end Q/K/V-aware device-algorithm co-design achieves an $8.93 \times$ energy-efficiency improvement over the baseline, highlighting the potential of M-GC CIM and DCIM for edge vision transformers (ViTs).