As the transistor area reaches the atomic scale, many technical challenges have occurred, jeopardizing the lifespan of DRAM scaling, of which word line (WL) resistive defects and Row hammer (R/H) failures are two of the most important quality problems. This paper introduces an innovative process technology to realize a high-purity and low-resistance cell WL that can solve two critical hurdles simultaneously, enabling the DRAM node of 12 nm and beyond. This technology verified a decrease in WL resistance by ∼50% and a two orders of magnitude improvement in R/H fail bits. In addition, by reducing interface trap density (Nit), significant enhancements in the on/off characteristic window and air transportation defects were obtained.

The intermittent single-bit (SB) failure is one of the most important problems in DRAM technology development because it is almost impossible to reproduce and screen out. In this paper, the intermittent SB failure was analyzed theoretically. Based on our physical modeling, we suggested several technical methods to reduce the intermittent SB failure and got the experimental results that decrease the intermittent SB failure rate. Furthermore, we predicted the failure rate based on our theoretical model. The SB failure rate had over 85% consistency between prediction and results. Therefore, we proved that our failure modeling is appropriate for predicting the occurrence of the intermittent SB failure. Furthermore, we can propose the design of the next generation DRAM technology to achieve equivalent or better intermittent SB quality than the previous generation from the beginning of the development.

DRAM devices are scaling down for decades to get advantages on higher density and cost effectiveness, however it is becoming more challenging to sustain the same (or improved) product quality within smaller dimension and storage capacitance. In particular, when the size decreases, the increase in the electric field and the decrease in the storage capacitance is inevitable, so a new structure change or extreme control of impurities is required. Chlorine is one of the most commonly used chemical element in DRAM fabrication process such as the etching and the deposition, however it makes interface traps and increases single-bit failures such as the retention failure and the bit flip by the row-hammering. In this paper, the effect of chlorine on actual characteristics was studied by measuring chlorine concentration and analyzing electrical characteristics. To reduce the damage from chlorine, we suggested three strategies and verified their effectiveness: (1) blocking the chlorine diffusion, (2) reducing the initial chlorine concentration in the storage capacitors, and (3) outgassing the chlorine by chemical reaction. We believe that if new schemes are applied using the above strategies, single bit characteristics can be improved.