In nanoimprint lithography (NIL), a residual layer inherently exists under the NIL resist features and must be removed in later etching steps. The subsequent etching process, known as breakthrough etching, leads to variations in the device pattern sizes and disrupts process integration because of NIL resist pattern loss. It was reported previously that the residual layer thickness (RLT) should be less than half the feature height (FH) for subsequent high-precision etching. In this work, we develop a one-pass etching process using an atomic-scale cycle stepped etching technique that passes through the residual layer to the spin-on-glass and demonstrate that the process can maintain the pattern width, regardless of RLT variations within the 12-32 nm thickness range. Even in the case of a 32-nm-thick RLT corresponding to 76% of the feature height (0.76 FH), good electrical performances were obtained without electrical failures in the half-pitch 26 nm line-and-space W-damascene interconnect patterns.

Nanoimprint lithography (NIL) is regarded as a promising technique for application to fabrication of the dual damascene structures that are commonly fabricated in back-end-of-line layers. Initial development work has commenced with a simple single-level process to evaluate the suitability of NIL for back-end processing applications. In this work, a test pattern with a minimum half-pitch of 24 nm was patterned using NIL, and W damascene interconnects were then fabricated via a combination of W deposition followed by chemical mechanical polishing. The electrical performances of the test devices were subsequently evaluated using the open/short test element group. The line resistances and leakage currents of the W interconnect structures fabricated using NIL showed good cumulative distributions at the designed minimum linewidth of 24 nm. We also demonstrated that a diagonal zigzag capacitor pattern with a pattern size of 2X nm showed good electrical properties.

Nanoimprint lithography (NIL) is a promising technique for fabricating dual damascene structures commonly fabricated in back-end-of-line layers. The feature size must be controlled for forming good open/short interconnects in damascene processes. In this work, we controlled the feature size by pattern transfer etching in NIL for half-pitch (HP) 24 nm damascene interconnects. By changing the conditions when transferring patterns etched in NIL to spin-on-carbon layers, the wiring dimensions were changed by approximately 5 nm for a HP 24 nm. A test pattern was fabricated by depositing tungsten, followed by chemical mechanical polishing. The electrical characteristics of test devices were subsequently evaluated using the open/short test element group. We widened the process window for fabricating damascene interconnects by varying the linewidth to control the feature size in pattern transfer etching.

Nanoimprint lithography (NIL) is attracting attention as a next-generation lithography technology. However, because NIL molds are patterned by electron beam lithography, it is difficult to fabricate NIL molds with a half-pitch (HP) of <= 15 nm. In this study, we demonstrated the possibility of fabricating NIL molds by the multi-patterning method, which is a self-aligned quadruple patterning (SAQP) technique. In the first step of the spacer double patterning, a SiO 2 layer is deposited on the mandrel HP 45-nm line and space (L/S) pattern of spin-on carbon by atomic layer deposition (ALD), followed by grating dry etching for the SiO 2 spacer. Transfer etching of the amorphous silicon (a-Si) layer and removal etching of SiO 2 using buffered hydrofluoric acid are subsequently performed. In the SAQP step, a SiO 2 layer as the spacer is deposited on the mandrel HP 22.5 nm L/S pattern of a-Si by ALD, followed by grating dry etching for the SiO 2 spacer. Using this method, we constructed the fabrication of HP 11.25 nm L/S patterns that can be applied to the NIL mold process.

Nanoimprint lithography (NIL) is promising for the processing of dual damascene structures fabricated in back-end-of-line layers, and initial development began with a simple single-level process to evaluate NIL's suitability. In this work, a test element group (TEG) pattern with a 70 nm half-pitch was selected, and copper (Cu) filling and chemical-mechanical polishing were performed after NIL pattern transfer. The results were compared with those obtained from the same TEG layout and processes but using ArF immersion lithography instead of NIL. Those obtained by NIL showed high pattern fidelity for all the designed layouts, whereas the resist patterns varied from the designed shape for ArF immersion lithography. The line resistances of Cu interconnects patterned by NIL showed good cumulative distributions at line widths ranging from 60 nm to 78 nm in 2 nm increments, without line breaks or space narrowing of SiO2. NIL showed potential for interconnect patterning with high-precision line width control.

We adopt a buried nanomagnet (BNM) technology on a one-dimensional (1D) array of silicon spin qubits, and its availability was investigated using numerical simulations. The qubit array is formed in the center of the Si fin and the nanomagnet is buried in the lower lateral part of the qubits. The nanomagnet placed near the qubit generates a strong slanting magnetic field in the qubit, enabling X-gate operation approximately 15 times faster than in conventional cases. Furthermore, the formation of a BNM using a self-aligned process suppresses the dimensional variation of the nanomagnet caused by process variation, thereby mitigating the slanting field fluctuation and fidelity degradation. In addition, even for multiple qubits formed in the Si fin, the BNM with excess length generated a uniform slanting field, mitigating fidelity degradation and enabling all qubits to operate using a single-frequency microwave. Therefore, the proposed structure is useful for 1D integrated structures.