Thin-channel silicon MOSFETs, such as nanosheet and complementary FET (CFET) architectures, have attracted significant attention as candidates for future highly integrated devices. In such devices, electron mobility exhibits trends that differ from those of conventional bulk MOSFETs, particularly as the channel thickness is reduced. To clarify the physical origin of these trends, the low-field phonon-limited electron mobility of single-gate and double-gate thin-channel silicon MOSFETs is systematically investigated as a function of channel thickness. Electron mobility is evaluated using a self-consistent solution of the Poisson-Schro & uml;dinger equations combined with a cellular-automaton-based transport framework. In single-gate MOSFETs, the weak-inversion mobility decreases for thin channels compared with bulk MOSFETs, whereas in double-gate MOSFETs, the mobility increases as the channel thickness decreases. These findings provide useful insights for future modeling and design considerations of advanced thin-channel MOSFETs.

The impact of a single interface trapped charge on threshold voltage (Vth) variation in a gate-all-around (GAA) nanosheet (NS) field effect transistors was evaluated using our custom 3D TCAD simulation framework. While silicon-on-insulator planar structures showed minimum dependence of Vth variation on silicon thickness, NS devices showed significantly high sensitivity. In NS architecture, Vth variation increased markedly as the silicon layer thickness was scaled down. The primary difference of the NS architecture was the presence of a channel distributed throughout the silicon sheet, enabled by the surrounding gates. At a thickness of 4 nm, the charge-induced potential extended to the counter-surface side, nearly eliminating the carrier path beneath the trapped charge. This impact was comparable to that caused by silicon thickness fluctuations with a few angstroms. These results suggest that in GAA architectures, silicon thickness scaling is a critical factor for evaluating Vth variation induced by trapped charges.

We have theoretically investigated the effect of an interface trap charge (ITC) on the Coulomb oscillation characteristics in a Si MOS-type quantum dot (Q-dot). We found that the ITC causes a variation in the fundamental characteristics of the Coulomb oscillation: a peak position, a peak height, and a peak interval. We clarified that the dependence of each variation on the ITC position is different from that of the other because of their different physical origins. We also discussed the amount of the peak position variation from the viewpoint of the operation of the Q-dots required in Si quantum computers (QCs). Mitigating the large variation caused by the ITC will be a critical issue for achieving large-scale Si QCs.

The requirements for the localization length and impurity positions of high-temperature quantum dot operations in isoelectronic-trap-assisted tunnel field-effect transistors (IET-TFETs) were investigated via device simulations. Charging strongly localized impurity levels induced an abrupt potential change, producing a high upper limit for the operation temperature. Strong Coulomb repulsion between a charged quantum dot and the surrounding electrons near the n-type source tended to hinder single-electron transistor operations. Therefore, a quantum dot near the p-type drain is favorable for high-temperature operations. This study clarifies the requirements for high-temperature quantum dot operations of IET-TFETs and promotes the development of high-temperature operable qubits.

We study the relationship between velocity overshoot (VO) and quantum confinement (QC) in electron transport in Si nanosheet (NS) gate-all-around (GAA) field-effect transistors (FETs) through device simulation. VO is incorporated into the simulation with an energy transport (ET) model, and QC with a density-gradient (DG) model. We measure the effects of VO on the NS FETs by comparing their static characteristics obtained with the ET model and with a drift–diffusion (DD) model, which essentially cannot consider VO, and then examine the differences in the VO effects between the cases with and without QC. VO increases the drain current, and QC enhances this increase by gathering electrons inside the NS. This enhancement increases as the gate length decreases, although it eventually begins to decrease. It also generally increases as the gate voltage decreases. However, it shows a more complex behavior for a change in NS thickness, depending on the gate length and gate voltage. These behaviors of the VO effect enhancement by QC can be well explained from the effective potential acting on electrons in the NS.

We adopt a buried nanomagnet (BNM) technology on a one-dimensional (1D) array of silicon spin qubits, and its availability was investigated using numerical simulations. The qubit array is formed in the center of the Si fin and the nanomagnet is buried in the lower lateral part of the qubits. The nanomagnet placed near the qubit generates a strong slanting magnetic field in the qubit, enabling X-gate operation approximately 15 times faster than in conventional cases. Furthermore, the formation of a BNM using a self-aligned process suppresses the dimensional variation of the nanomagnet caused by process variation, thereby mitigating the slanting field fluctuation and fidelity degradation. In addition, even for multiple qubits formed in the Si fin, the BNM with excess length generated a uniform slanting field, mitigating fidelity degradation and enabling all qubits to operate using a single-frequency microwave. Therefore, the proposed structure is useful for 1D integrated structures.

The study aimed to theoretically investigate the transfer characteristics of MOSFETs at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our Technology Computer Aided Design (TCAD) simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V t) in the low drain voltage (V d) region, which causes the misestimation of the DIBL parameter. This V t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation in such underlap devices, confirming the dependence of the DIBL parameter on the linear region of V d serves as an effective method to ensure accurate estimation.

In this study, we propose technologies for the device structure, gate fabrication process, and back-bias-assisted operation of Si spin qubits to realize the high robustness of the two-qubit SWAP gate operation against process variations. We performed quantum device simulations for MOS-type two-qubit devices and verified the benefits of these technologies on the SWAP gate fidelity. We clarified that these technologies significantly improve the robustness of the SWAP gate operation against process variations and achieve a 6 σ -yield SWAP gate operation with 99% fidelity, assuming device size fluctuation of the International Roadmap for Devices and Systems (IRDS) target for 2022. The proposed technologies provide a solution for completing a universal quantum gate set for realizing universal quantum computers with silicon.

We simulate the static behavior of Ge-p/Si-n nanosheet complementary FETs (CFETs), where p-type FETs containing Ge nanosheet channels are stacked on top of n-type FETs containing Si nanosheet channels, and we investigate its relation to temperature while comparing it with that of Si-p/Si-n nanosheet CFETs, whose p-type FETs contain Si nanosheet channels. It is found that temperature rise has similar effects on the static characteristics of the two CFETs operating as inverters, although the variations in threshold voltage and noise margin with rising temperature are slightly smaller in the Ge-p/Si-n CFET inverter than in the Si-p/Si-n CFET inverter. The temperature rise effects are fully explained by the temperature dependence of material and carrier properties of Ge and Si.

Increased threshold voltages have been observed during linear-mode operation of short-channel bulk metal-oxide-semiconductor field-effect transistors (MOSFETs) employing shallow source and drain extension technology at cryogenic temperatures. These increases were suppressed during saturation-mode operation, which resulted in the increase of a threshold voltage variation between linear- and saturation-modes as if drain-induced barrier lowering occurred. Numerical simulations revealed that these increases originate from enhanced depletion in the extension region and subsequent increases in channel resistance at cryogenic temperatures. These data suggest that shallow extensions should be designed more carefully in the case of MOSFETs intended for cryogenic operation.

We consider a method to simulate heat transport by phonons together with charge transport by electrons and holes that is applicable to standard technology computer-aided design (TCAD) simulators. Because our proposed method handles each phonon mode separately, it can connect the atomistic calculation of phonon properties of materials directly to the TCAD simulation of the thermal behavior of semiconductor devices. We implement this method in our homemade TCAD and simulate heat generation and transport in a transistor with a thin silicon-on-insulator body using the phonon properties of Si obtained from lattice dynamics calculations. The same simulation is carried out with phonon heat transport approximated by the heat equation, and the results indicate that it is difficult for the heat equation to accurately reproduce the phonon heat transport.

GaN-based high electron mobility transistors (HEMTs) are expected to have high performance in base station applications. Recently, it was reported that the combination of the Poisson–Schrödinger method and cellular automaton method is effective for predicting the mobility of channel two-dimensional electron gas of GaN HEMTs. In the operation condition of HEMT, the surface electron density of the channel is on the order of 1013 cm−2, and the effect of degeneracy cannot be ignored in calculating the mobility. Since the electron distribution function is always stably obtained by the cellular automaton method, the degeneracy effect can be considered stably. In this paper, through the comparison of different degeneracy evaluation methods, the anisotropy of the electron distribution function under the electric field acceleration is clarified to affect the HEMT mobility prediction significantly.

We propose a buried nanomagnet (BNM) realizing high-speed/low-variability silicon spin qubit operation, inspired by buried wiring technology, for the first time. High-speed quantum-gate operation results from large slanting magnetic-field generated by the BNM disposed quite close to a spin qubit, and low-variation of fidelity thanks to the self-aligned fabrication process. Employing TCAD-based simulation, we demonstrate that the BNM realizes 10 times faster Rabi oscillation (faster spin-flip) than previous works and >99% fidelity under certain process variations. Also, the proposed BNM arrangement is implementable for error-correctable large-scale quantum computers employing a 2D-latticed qubit layout. This technology paves the way to practical large-scale quantum computers with silicon.

GaN HEMTs are expected to achieve better device performance for microwave applications. The cellular automaton method is effective for predicting the transport characteristics of the two-dimensional electron gas, which is the key to the HEMT device performance. To predict the mobility of two-dimensional electron gas, it is necessary to consider the physics of the subbands. Since the traditional powerful Monte Carlo method selects the electron scattering mechanism by random numbers, it is necessary to suppress statistical problems to obtain a stable solution. We confirmed that our approach that combines the Poisson-Schrodinger and the cellular automaton method enables seamless and stable mobility calculations over a wide temperature range including low temperatures. In this paper, the temperature-dependent electron mobility of GaN HEMT calculated with and without interface roughness scattering model is studied.