This implementation strategy enables incremental test of all system components, providing an alternative solution to the known good die testing problem. The authors present a simple microcontroller emulator designed and fabricated for study of the test logic needed as a key component of this method.<>

This paper presents a cost-based methodology for assessing the effectiveness of various MCM implementation strategies. It is focused on testing. Two approaches to the MCM testing problem are investigated in detail. One is based on the assumption that system components are perfect(“known good die” approach) and the other uses the “smart substrate” concept. An MCM using a smart substrate is one in which the substrate contains active circuitry for carrying out testing functions. For these two testing options, the obtained results suggest the existence of “windows of opportunity” for both KGD and smart substrate solutions

In the semiconductor industry progress has been achieved by building fablines that implement smaller feature sizes. This successful strategy has produced a constant decrease in cost and improvcment in performance with a resultant constant increase in the cost of fablines. These heavy investments can be justified by high volume or large profit products. However, many medium volume manufacturers can not compete with "larger-volume" or "cash-rich" competitors. This paper will focus on a strategy to minimize the cost of manufacturing based on a product complexity oriented cost modeling technique.

This paper demonstrates the need for specialized test structures and algorithms to obtain defect characteristics which are necessary for accurate yield prediction. Using one such specialized test structure, a general methodology for extracting size distribution parameters for both shorts and opens in any IC layer, which is independent of defect and yield models, is developed in this paper. The application of this methodology is illustrated by means of a fabrication experiment.

Interconnects will dictate the high speed microwave operation of future VLSI circuits. Even though Si VLSI devices with ft in excess of 15 GHz have been reported in the literature, the realization of this performance level is limited. This is due to: (1) the response time and integration density of traditional interconnect technologies (coplanar waveguides, striplines, etc.); and (2) the crosstalk between different interconnect lines, particularly if the metal pitch is decreased to 1 μm or less. A fabrication technique which alleviates this impasse via the construction of multilevel microcoaxial interconnects (M2CI) has been reported. This technology is compatible with existing VLSI processes while maintaining existing interconnect densities. In this paper, the progress to date in developing this technology along with a methodology for the electrical and mechanical characterization of fabricated microcoaxial lines is presented. This includes: (a) the mechanical properties of the microcoaxial lines; (b) the characteristic impedance and its relation to line parameters. Testing to date indicates the successful fabrication of 5 Ω coaxial lines having very small cross sectional areas. Finally, potential VLSI applications of this technology are described

A description is given of the application of mechanical planarization to the interlevel dielectric (ILD) of a multilevel interconnect system. Experimental results obtained from large 80K, two-level metal CMOS gate arrays (0.7 cm2) having mechanically planarized ILD indicated leveling lengths on the order of 0.5 cm and excellent via functionality. Surface leveling with variations of less than 200 Å was readily achieved over the whole gate array die. No detrimental effects were observed in a fully functional die when compared with devices using sacrificial spin-on glass. The results of this study indicate that mechanical planarization will make a critical contribution to the fabrication of ULSI devices having 0.25-μm interconnect feature sizes

A square-wave test structure is described which provides a useful vehicle for characterizing planarization processes. The structure is designed for easy replication in different laboratories to allow comparison of planarization methods in spite of their inherent pattern sensitivity. Results obtained for a number of mechanical planarization processes on this structure are presented. A planarization rate parameter p is defined and used to describe the planarization of features in the width range of 1-10 mm, a range which is important because of the effects of long-range pattern density variations in VLSI chips. Polishing pad structure and condition are found to be the most important determiners of p, and results for several commercially available pads are reported. Mechanical planarization adequate to handle the interlayer dielectric (ILD) planarization requirements of most chips is demonstrated

A novel interconnect scheme is presented which allows the fabrication of microwave microcoaxial interconnect (M/sup 2/CI) structures. This technology offers full compatibility with existing VLSI processes, tailor matching of characteristic impedance, and crosstalk-free interconnects. The present status of this technology is reviewed. It is noted that the implementation of this technique should substantially improve the present speed limitation imposed by multilevel wiring and open a new performance window for high-density VLSI devices.<>

Cu films between 1000 AA and 1 mu m thick were deposited from an electroless Cu plating bath on various metal seed layers. The bulk resistivity of Cu films was a function of the film thickness. For thin films of 1000 AA, the electrical resistivity was three times greater than reported bulk values. For 1- mu m films, resistivities of 2.3 mu Omega -cm were obtained. This larger resistivity is apparently influenced by defects grown into the film. The electrical and physical properties of these films were examined after rapid thermal processing at temperatures of up to 900 degrees C on inert substrates. Transmission electron microscope (TEM) analyses indicated changes in grain size from 600 AA to 2500 AA. Thin layers of FCC metals in contact with Cu, such as Ni or Pt, were detrimental to the electrical resistivity after moderate thermal processing. These interactions could be easily predicted from phase diagrams of Cu with other FCC metals and indicate that Ni encapsulation of Cu is impractical. Selective Cu deposition into dielectric channels on seed layers was found to be clean with little if any random field nucleation. Copper that was selectively deposited into contacts of a test gate array exhibited electrical continuity on CVD W but showed contact resistances substantially larger than standard metallurgies.< >