Low-power high-speed transceivers are critical for data-centers and supercomputers to host the rapid growing artificial intelligent applications. Recently, the market demand for 800G transceivers surges thanks to its ability to support higher rate and lower latency data transmission [5] [6] [20] [23]. However, aggressive power budget imposed by optical module's tight thermal constraint and data center's operating cost poses great challenges for the transceiver design. This work presents a low power DSP-based single-chip 800GbE PAM-4 PHY transceiver in 7nm FinFET technology capable of driving eight lanes of up to 112.5Gb/s. It supports both electrical and optical links with monolithic integrated laser driver enabling direct-drive PAM-4 output capability for EML and silicon photonics. Thanks to both architecture level and circuit level innovations, this work achieves pre-FEC BER<3E-8 under 42dB channel with 2.59pJ/b analog power efficiency, which is the best power-efficiency among the published 112Gb/s and 224Gb/s transceivers. The integration of high-swing driver enables significant power savings against the conventional stand-alone laser driver solutions.

This work presents a low power DSP-based single-chip 800GbE PAM-4 PHY transceiver in 7 nm process capable of driving eight lanes of up to 112-Gb/s. It supports both electrical and optical links with monolithic integrated laser driver enabling direct-drive PAM-4 output capability for EML and silicon photonics. The transceiver supports 42 dB IL channel at Nyquist with pre-FEC BER<3E-8. The per-lane analog power efficiency is 2.59pJ/b for low-swing drive mode and 4.58 pJ/b for direct-drive mode.

The rapid growth of data center traffic, driven by cloud technology adoption, has propelled the development of a variety of spectrally efficient modulation formats, such as 4-level pulse amplitude modulation (PAM4), quadrature phase shift keying (QPSK) and quadrature amplitude modulation (QAM). High speed CMOS DSP-based transceivers provide complex equalization scheme to compensate for the channel loss as well as the nonlinearity impairments introduced by chromatic and polarization dispersion. The recent development of ultra-high speed data converters has been a key enabling technology converting data signal between analog and digital domain, which has shaped the traditional communication transceiver systems. This paper covers the advancement of CMOS data converter technology and its wide application, as well as the future development and trend.

At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated with high-sampling-rate data converters are critical to realize the phase-sensitive modulation schemes based on coherent detection that are essential to metro and long-haul networks [1]. To support dual-polarization QPSK format, quad low-power DACs and ADCs are needed and precise phase alignment has to be maintained between XI, XQ, YI, and YQ channels, in order to transmit and extract the phase information in the coherent system, as shown in Fig. 29.2.1. For long-haul transmission at 100Gb/s, because of the FEC overhead, the baud rate per channel can be as high as 32Gb/s. In addition, the receiver often requires double sampling at 64GS/s for robust clock-data recovery and SNR improvement for stressed channels. Double sampling also enables the DSP to implement more complicated equalization schemes and more flexible spectrum engineering at high frequency on the transmitter side. This paper reports the receiver and transmitter fully integrated in a 100G coherent DSP chip, using 4×64GS/s ADCs and DACs with 8b resolution, fabricated in a standard 20nm CMOS process.