Low-power high-speed transceivers are critical for data-centers and supercomputers to host the rapid growing artificial intelligent applications. Recently, the market demand for 800G transceivers surges thanks to its ability to support higher rate and lower latency data transmission [5] [6] [20] [23]. However, aggressive power budget imposed by optical module's tight thermal constraint and data center's operating cost poses great challenges for the transceiver design. This work presents a low power DSP-based single-chip 800GbE PAM-4 PHY transceiver in 7nm FinFET technology capable of driving eight lanes of up to 112.5Gb/s. It supports both electrical and optical links with monolithic integrated laser driver enabling direct-drive PAM-4 output capability for EML and silicon photonics. Thanks to both architecture level and circuit level innovations, this work achieves pre-FEC BER<3E-8 under 42dB channel with 2.59pJ/b analog power efficiency, which is the best power-efficiency among the published 112Gb/s and 224Gb/s transceivers. The integration of high-swing driver enables significant power savings against the conventional stand-alone laser driver solutions.

The rapid growth of data center traffic, driven by cloud technology adoption, has propelled the development of a variety of spectrally efficient modulation formats, such as 4-level pulse amplitude modulation (PAM4), quadrature phase shift keying (QPSK) and quadrature amplitude modulation (QAM). High speed CMOS DSP-based transceivers provide complex equalization scheme to compensate for the channel loss as well as the nonlinearity impairments introduced by chromatic and polarization dispersion. The recent development of ultra-high speed data converters has been a key enabling technology converting data signal between analog and digital domain, which has shaped the traditional communication transceiver systems. This paper covers the advancement of CMOS data converter technology and its wide application, as well as the future development and trend.

At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated with high-sampling-rate data converters are critical to realize the phase-sensitive modulation schemes based on coherent detection that are essential to metro and long-haul networks [1]. To support dual-polarization QPSK format, quad low-power DACs and ADCs are needed and precise phase alignment has to be maintained between XI, XQ, YI, and YQ channels, in order to transmit and extract the phase information in the coherent system, as shown in Fig. 29.2.1. For long-haul transmission at 100Gb/s, because of the FEC overhead, the baud rate per channel can be as high as 32Gb/s. In addition, the receiver often requires double sampling at 64GS/s for robust clock-data recovery and SNR improvement for stressed channels. Double sampling also enables the DSP to implement more complicated equalization schemes and more flexible spectrum engineering at high frequency on the transmitter side. This paper reports the receiver and transmitter fully integrated in a 100G coherent DSP chip, using 4×64GS/s ADCs and DACs with 8b resolution, fabricated in a standard 20nm CMOS process.

Multilevel modulation formats, such as PAM-4, have been introduced in recent years for next generation wireline communication systems for more efficient use of the available link bandwidth. High-speed ADCs with digital signal processing (DSP) can provide robust performance for such systems to compensate for the severe channel impairment as the data rate continues to increase.

At data rates beyond 10Gb/s, most wireline links employ NRZ signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more severe and do not benefit from process scaling in the same fashion that circuit design does. Reflections from impedance discontinuities in the PCB and package caused by vias and connectors introduce significant signal loss and distortions at higher frequencies. Even with an ideal channel, at every package-die interface, there is an intrinsic parasitic capacitance due to the pads and the ESD circuit amounting to at least 150fF, and a 50Ω resistor termination at both the transmit and receive ends resulting in an intrinsic pole at 23GHz or lower. In light of all these limitations, serial NRZ signaling beyond 60Gb/s appears suboptimal in terms of both power and performance. Utilizing various modulation techniques such as PAM4, one can achieve a higher spectral efficiency [2]. To enable such transmission formats, high-speed moderate-resolution data converters are required. This paper describes a 36Gb/s transmitter based on an 18GS/s 8b DAC implemented in 28nm CMOS, compliant to the new IEEE802.3bj standard for 100G Ethernet over backplane and copper cables [3].

This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology. Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2-6.8Gb/s while supporting a wide range of communication standards, including SGMII, QSGMII, PCIE, SATA, USB3, XAUI and RXAUI. Power consumption per lane is 23mW at 0.9V for SATA3 at 6Gb/s, with an area of 0.265mm2 for a single-lane transceiver with PLL.

This paper presents a wide-band analog Fractional-N clock synthesizer operating from 8 to 12.4GHz suited for data communication standards. The synthesizer generates a low noise clock with rms jitter of 288-460fs, yet maintains wide loop bandwidth from 1.5 to 4.3MHz. The design consumes 16.9mW from a 1V supply, while occupying an area of 0.39mm2 in a 40nm CMOS technology.

An 8.0 GHz to 12.2 GHz PLL with a capacitor multiplier-based active loop filter is designed in a 28 nm digital CMOS process. A passive loop filter-based version of the PLL is also implemented for comparison. While the PLL area is comparable to that of digital PLLs, the PLL performance is as good as that of an analog PLL that employs a passive loop filter. The capacitor multiplier-based active loop filter PLL has a jitter performance of 198 fs (rms), while its passive loop filter-based counterpart shows a jitter performance of 195 fs (rms). The PLL occupies 0.093 mm(2) and consumes 15.5 mA at 1.0V.

A SerDes operating from 8.5 to 11.4 Gb/s using nearly all CMOS digital circuits is presented. The transmitter achieves up to 1 Vdpp output swing with a DDJ as low as 2.7 ps. The receiver achieves an input sensitivity of less than 17 mVdpp. The chip is capable of transmitting and receiving data on an FR4 channel with 21 dB loss at Nyquist at a BER <; 10-12. The power consumption per Tx/Rx pair is 28.5 mW, and the active area is 0.047 mm2 in 28 nm CMOS. The chip reports the minimum SerDes area in the published literature.

A 39.8-44.6 Gb/s transmitter and receiver chipset designed in 40 nm CMOS is presented. The line-side TX implements a 2-tap FIR filter with delay-based pre-emphasis. The line-side RX uses a quarter-rate CDR architecture. The TX output shows 0.9 ps pp ISI and 0.2 ps rms RJ at 0.87 W. The RX achieves a jitter tolerance of 0.6 UI pp at 100 MHz and an input sensitivity of 20 mV pp\mathchar"702D diff at 1.05 W. The combined transmitter/receiver equalization enables 44.6 Gb/s data transmission using 2 31 -1 PRBS at BER 10 -12 over a channel with >21 dB loss at Nyquist frequency.

This paper proposes the use of N-push operation for combining the functions of the VCO and divider in the mm-wave frequency range. If employed in a PLL, the combined VCO/divider (C-VCO/D) would potentially provide wider tuning range than traditional mm-wave PLLs employing injection locked frequency dividers, thus exploiting the full range available in the 60 GHz band (57 GHz-64 GHz). The behavior of triple push oscillators based on injection locking theory is analyzed to study their various oscillation modes, their stability and the effect of mismatch on the oscillator performance. Design guidelines are provided for boosting the third harmonic power at a given power budget. Using 130 nm IBM CMOS technology, multiple versions of the triple push oscillator are implemented and characterized. A 55 GHz-65 GHz tuning range is obtained using a 206 pH tank inductance and requires I core = 20 mA, and I buffer = 15 mA from a 1.4 V supply. For a tank inductance of 140 pH, a 63.2 GHz-72.4 GHz tuning range is obtained using I core = 17 mA, and I buffer = 18 mA with a phase noise of -91 dBc/Hz at 10 MHz from the 63.2 GHz carrier and -95 dBc/Hz at 10 MHz from the 72.4 GHz carrier.

A frequency synthesizer architecture is presented, which alleviates the problems in the interaction between the VCO and the divider in typical mm-wave synthesizers. The presented architecture eliminates the need for an injection locked frequency divider, by creating a direct by-pass path from mm-wave VCO to the static dividers, improving the operation range of the synthesizer. The designed 60 GHz CMOS PLL is based on a triple-push VCO, which acts as a combined mm-wave VCO and divider (C-VCO/D). A systematic design flow that links device level to system level is presented for noise and dynamic performance optimization. The paper also highlights design considerations and floor planning issues associated with mm-wave PLLs based on Npush oscillators. The validity of the concept is supported by simulation results.

This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a typical multi-band oscillator. The relation between the coupling coefficient of the transformer load, selection of frequency bands, and the resulting quality factor at each band is investigated. The concept is validated through measurement results from a prototype fabricated in 0.25 ¿m CMOS technology. The VCO has a measured tuning range of 1.94 to 2.55 GHz for the low frequency range and 3.6 to 4.77 GHz for the high frequency range. It draws a current of 1 mA from 1.8 V supply with a measured phase noise of -116 dBc/Hz at 1 MHz offset from a 2.55 GHz carrier. For the high frequency band, the VCO draws 10.1 mA from the same supply with a phase noise of -122.8 dBc/Hz at 1 MHz offset from a 4.77 GHz carrier.