The authors propose a novel stacked capacitor cell with dual cell plate (DCP cell) for 64-Mb DRAMs. The major advantage of this cell is that the dual cell plates completely surround the whole surface of the storage polysilicon, and the storage capacitance of this cell increases significantly compared to the conventional stacked capacitor cell. For a 1.3- mu m/sup 2/ cell, the DCP cell should achieve a storage capacitance of more than 25 fF. The experimental results indicate that the DCP cell can realize the 64-Mb DRAMs and 1.3- mu m/sup 2/ cell area using the 0.3- mu m design rule.<>

A novel isolation technology, called buried insulator between source/drain polysilicon (BIPS), is described. The BIPS isolation structure consists of refilling CVD (chemical vapor deposition) oxides in openings between source/drain polysilicon patterns by double photoresist etchback. A defect- and bird's beak-free process can be realized by this isolation. Devices with BIPS isolation are compared with LOCOS (local oxidation of silicon) with respect to isolation parasitic effects and current drive capability. A 0.5- mu m isolation is achieved, and the narrow channel effects are almost suppressed with BIPS isolation. The subthreshold characteristics of devices with BIPS isolation give the same shape value as those for conventional devices with LOCOS isolation. A ring oscillator with BIPS isolation exhibits a propagation delay time of 69 ps/gate.<>