Model-based optical proximity correction (MB-OPC) has been widely applied in advanced lithography processes today. As k1 factor decreases and circuit design complexity increases, various advanced OPC modeling techniques have been employed to better simulate the lithography processes, such as mask3D (M3D), negative tone development (NTD) modeling techniques, etc. These advanced OPC modeling techniques introduce increasingly nonlinear behaviors in MB-OPC and bring many challenges in controlling edge placement error (EPE) and critical dimension (CD) while maintaining non-aggressive mask correction where possible for mask-rule check (MRC) compliance and better yield. In this paper, we review the MB-OPC challenges, and show our integration of Proteus inverse lithography technology (ILT) with MB-OPC as the solution to these challenges.

Traditional rule-based and model-based Optical Proximity Correction (OPC) and rule-based Resolution Enhancement Technology (RET) methods have been the workhorse mask synthesis methods in volume production for logic and memory devices for more than 15 years. With continuous technical enhancements, these methods have proven themselves robust, flexible and fast enough to meet many of the technical needs of even the most advanced nodes. Inverse Lithography Technology (ILT) methods are well known to have strong benefits in finding flexible mask pattern solutions to improve process window for the most advanced design locations where traditional methods are not sufficient. However, OPC/RET requirements at each node have changed radically in the last 15 years beyond just technical requirements. The volume of engineering work to be done has also skyrocketed. The number of device layers which need OPC/RET can be 10X higher than in earlier nodes. Additionally, the number of mask layers per device layer is often 2X or more times higher with multiple patterning. Finally, the number of features to correct per mask increases ~2X with each node. These factors led to a large increase in the number of OPC engineers needed to develop the complex new OPC/RET recipes for advanced nodes. In this paper, we describe new developments which significantly improve the productivity of OPC engineers to deploy Rule Based OPC (RBOPC), Model Based OPC (MBOPC), AF, and ILT recipes in modern manufacturing flows. In addition to technical improvements such as novel multiple segment hot-spot fixing solvers and ILT hot-spot fixing necessary to support correction needs, we have re-architected the entire flow based on how OPC engineers now develop and maintain OPC/RET recipes. This improved OPC/RET development methodology includes specifically targeted advanced new technical functions; new types of modular structures for much faster reuse of customizations; and new interfaces to flexible programming capabilities to enable easier development and integration of deep customizations for the most challenging technical needs.

Traditional model-based Optical Proximity Correction (OPC) and rule-based Resolution Enhancement Technology (RET) methods have been the workhorse mask synthesis methods in volume production for logic and memory devices for more than 15 years. Rule-based OPC methods have been in standard use for over 20 years now. With continuous technical enhancements, these methods have proven themselves robust, flexible and fast enough to meet many of the technical needs of even the most advanced nodes. Inverse Lithography Technology (ILT) methods are well known to have strong benefits in finding flexible mask pattern solutions to improve process window for the most advanced design locations where traditional methods are not sufficient. However, OPC/RET requirements at each node have changed radically in the last 20 years beyond just technical requirements. The volume of engineering work to be done has also skyrocketed. The number of device layers which need OPC/RET can be 10X higher than in earlier nodes. Additionally, the number of mask layers per device layer is often 2X or more times higher with multiple patterning. Finally, the number of features to correct per mask increases ~2X with each node. These factors led to a large increase in the number of OPC engineers needed to develop the complex new OPC/RET recipes for advanced nodes. In this paper, we describe new developments which significantly improve the productivity of OPC engineers to deploy Rule Based OPC (RBOPC), Model Based OPC (MBOPC), AF, and ILT recipes in modern manufacturing flows. In addition to technical improvements such as novel multiple segment hotspot fixing solvers and ILT hot-spot fixing necessary to support correction needs, we have re-architected the entire flow based on how OPC engineers now develop and maintain OPC/RET recipes. The re-architecture of the flow takes advantages of more recent developments in modular and structured programming methods which are known to benefit ease engineering software development applications. Therefore, this improved OPC/RET development methodology includes specifically targeted advanced new technical functions; new types of modular structures for much faster reuse of customizations; and new interfaces to flexible programming capabilities to enable easier development and integration of deep customizations for the most challenging technical needs.

Traditional segment-based model-based OPC methods have been the mainstream mask layout optimization techniques in volume production for memory and embedded memory devices for many device generations. These techniques have been continually optimized over time to meet the ever increasing difficulties of memory and memory periphery patterning. There are a range of difficult issues for patterning embedded memories successfully. These difficulties include the need for a very high level of symmetry and consistency (both within memory cells themselves and between cells) due to circuit effects such as noise margin requirements in SRAMs.Memory cells and access structures consume a large percentage of area in embedded devices so there is a very high return from shrinking the cell area as much as possible. This aggressive scaling leads to very difficult resolution, 2D CD control and process window requirements. Additionally, the range of interactions between mask synthesis corrections of neighboring areas can extend well beyond the size of the memory cell, making it difficult to fully take advantage of the inherent designed cell hierarchy in mask pattern optimization. This is especially true for non-traditional (i.e., less dependent on geometric rule) OPC/RET methods such as inverse lithography techniques (ILT) which inherently have more model-based decisions in their optimizations.New inverse methods such as model-based SRAF placement and ILT are, however, well known to have considerable benefits in finding flexible mask pattern solutions to improve process window, improve 2D CD control, and improve resolution in ultra-dense memory patterns. They also are known to reduce recipe complexity and provide native MRC compliant mask pattern solutions. Unfortunately, ILT is also known to be several times slower than traditional OPC methods due to the increased computational lithographic optimizations it performs.In this paper, we describe and present results for a methodology to greatly improve the ability of ILT to optimize advanced embedded memory designs while retaining significant hierarchy and cell design symmetry, therefore, have good turnaround time and CD uniformity. This paper will explain the enhancements which have been developed in order to overcome the traditional difficulties listed above. These enhancements are in the categories of local CD control, global chip processing options, process window benefit, turn-around time and hierarchy retention.

Model-driven target optimization using an ILT hotspot fixer is applied to line collapsing defects of 2- dimensional randomtest pattern of a very low K1 process. The target is moved by minimizing the process variation band and the pitches of hotspot points are relaxed.The image quality improvement is thenchecked. Model driven target optimized NILS and MEEF at the weakest hotspot point are improved to 1.22 and 5.5 from the values 0.79 and 10.6 of a traditional OPCwith advanced solver, respectively. The pattern collapsing hotspot is then validated to be repaired by optimizing target position. A full hotspot fixer flow including model-driven target optimization using ILT can also be extended into DFM applications.

Patterning of contact hole using KrF lithography system for the sub 90nm technology node is one of the most challenging tasks. Contact hole pattern can be printed using Off-Axis Illumination(OAI) such as dipole or Quasar or Quadrupole at KrF lithography system. However this condition usually offer poor image contrast and poor Depth Of Focus(DOF), especially isolated contact hole. Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip CD variation reduction. The insertion of SRAF in a contact design is mostly done using rule based scripting. However the rule based SRAF strategy that has been followed historically is not always able to increase the process window of these 'forbidden pitches' sufficiently to allow sustainable manufacturing. Especially in case of random contact hole, rule-based SRAF placement is almost impossible task. We have used an inverse lithography technique to treat random contact hole. In this paper we proved the impact of SRAF configuration. Inverse lithography technique was successfully used to treat random contact holes. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described. As a conclusion, we suggest methodology to set up optimum SRAF configuration with rule and inverse lithography technology.

The contact layer for the 22 nm logic node faces many technological hurdles. Even using techniques such as multiple-exposure patterning and 193 nm immersion, it will be difficult to achieve the depth of focus and CD uniformity required for 22 nm production. Such difficulties can be mitigated by recent advances in Inverse Lithography Technology (ILT). For example, circular main features combined with complex curvilinear assist features can provide superior CD uniformity with the required depth of focus, particularly for isolated contacts. However, such a solution can lead to long mask write times, because the curvilinear shapes necessitate a higher shot count induced by inefficient data fracturing, even without considering the circular main features. The current approach is to Manhattanize the curvilinear features resulting in a nearly equivalent image quality on the wafer; but a further reduction in mask write times could help lower costs. This paper describes a novel mask-writing method that uses a production e-beam mask writer to write main features as circles, with curvilinear assist features, while reducing shot count compared to traditional Manhattanized masks. As a result the new method makes manufacturing of ideal ILT-type masks feasible from a technical as well as from an economic standpoint. Resist-exposed SEM images are presented that validate the new method.

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance than traditional OPC masks. To enable ILT for production as one of the leading candidates for low-k1 lithography, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications[4,5], it has been shown that the Inverse Synthesizer (ISTM) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT has been demonstrated at full-chip level. To fully integrate ILT mask into production, a number of areas were investigated to further reduce ILT mask complexity without compromising too much of process window. These areas include flexible controls of SRAF placements with respect to local feature sizes, separate control of Manhattan mask segment length of main and SRAF features, topology based variable segmentation length, and jog alignment. The impact of these approaches on e-beam mask writing time and lithography performance is presented in the paper.

To enable Inverse Lithography Technology (ILT) for production as one of the leading candidates for low-k1 lithography at 32nm and below, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications[1,2], it has been shown that the Inverse Synthesizer (ISTM) produces ILT full chip mask of contact layer with comparable mask write time with conventional OPC while maintaining the significant litho gains of ILT mask. To fully integrate ILT masks into production for all layers including line and space layers such as poly layer, a number of areas were investigated to further reduce ILT mask complexity and total e-beam shot count. These areas include flexible controls of SRAF placements with respect to local feature sizes, improved Manhattan algorithm, topology based variable Manhattan segmentation, jog alignment and mask data fracture optimization. The impact of these approaches on e-beam shot count and lithography performance of ILT masks is presented in the paper.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. Inspection presents another great challenge; Most mask rules are imposed not because of mask manufacturing constraints, but due to limitations of mask inspection tools. In addition, at the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs), ILT, and SMO are required. Their use results in significantly increased mask complexity, making mask defect inspection and disposition more challenging than ever. In this paper, a single computational lithography and computational inspection framework based on Level Set Method is presented and explained in non-mathematical language. Results at the 32nm node and below are presented which demonstrate the benefits of Level-Set-Method-based ILT and IIT in design rule optimization, SMO, full-chip correction, and mask inspection.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below -lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. In this paper a single computational lithography framework for design, mask, and source co-optimization will be explained in non-mathematical language. A number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of Level-Set-Method-based ILT in applications covering design rule optimization, SMO, and full-chip correction.

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task.To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

In the first implimentation by Luminescent of ILT-enabled Source-Mask Optimization (SMO), an ILT-optimized mask was generated for each designated illumination condition as the source was swept through various parameter settings in order to find the best combination of source and mask. This approach has been successfully applied to explore and select lithography processes and design rules for advanced semiconductor technology nodes. In Luminescent's latest implimentation of ILT-enabled SMO, the same Level Set Method used in the mask optimization is used in the source optimization; in other words, the source map is represented by a level set function. During the optimization process, the level set function evolves to achieve a minimized cost function, where the cost function is defined as the difference between aerial image and ideal image (MEEF and DOF can also be used in the cost function) via a gradient flow, and the gradient flow is based on the cost function itself. This flow is interlaceded with the mask inversion flow so that a simultaneous mask & source co-optimization is achieved. In this paper a number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of ILT-enabled SMO.

At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. This paper describes how mask patterns can first be recovered from the inspection images by applying patented algorithms that employ Level Set Methods. The mask pattern recovery step is followed by aerial/wafer image simulation, the results of which can be plugged into an automated mask defect disposition system based on aerial/wafer image. The disposition criteria are primarily based on wafer-plane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, for use in mask defect disposition as well. Results on both programmed defects and production defects collected at Samsung's mask shop are presented which demonstrate the accuracy and consistency of using the Level Set Methods and aerial/wafer image based automated mask disposition.

Masks computed by use of Inverse Lithography Technology (ILT) are being increasingly used in 32nm and below nodes for their significantly better litho performance outperforming model-based OPC [1,2]. This technique poses the design of photomasks as an inverse problem and then solves for the optimal photomask using rigorous mathematical approach [3,4]. One such approach is the level set based method [5] wherein a level set function φ(x,y) is made to represent the contour of the mask. The zero level set φ(x,y)=0 then represents the actual mask at a given instance. The same level-set technique has now been extended to determine the most optimized source φ(p,q) for a given target or mask. Cooptimization of both the source and mask is a natural extension of optimizing the mask alone in ILT. The same cost function, say maximizing DOF, which is used to compute the ILT mask can be used for the source optimization as well. This approach enables accurate and fast computation of the optimized source and mask for given set of patterns and also utilizes running on a distributed computing environment. In this paper, the level set based SMO approach will be first validated on simple contact array patterns and then extended to the optimization of sample 22nm logic contact design patterns, including array, SRAM and random logic. The effect of using different emphasis in defining the cost function will also be studied.

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.

At the most advanced technology nodes, such as 32nm and 22nm, aggressive OPC and Sub-Resolution Assist Features (SRAFs) are required. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. This paper describes how mask patterns can first be recovered from the inspection images by applying patented algorithms using Level Set Methods. The mask pattern recovery step is then followed by aerial/wafer image simulation, the results of which can be plugged into an automated mask defect disposition system based on aerial/wafer image. The disposition criteria are primarily based on wafer-plane CD variance. The system also connects to a post-OPC lithography verification tool that can provide gauges and CD specs, thereby enabling them to be used in mask defect disposition as well. Results on both programmed defects and production defects collected at Samsung mask shop are presented to show the accuracy and consistency of using the Level Set Methods and aerial/wafer image based automated mask disposition.

Mask Error Enhancement Factor (MEEF) plays an increasingly important role in the DFM flow required to continue shrinking designs in the low-k1 lithography regime. The ability to understand and minimize MEEF during design optimization and RET application is essential to obtain a usable process window. The traditional limited-cutline approach to analyzing and characterizing MEEF is no longer sufficient to accommodate increasing design complexity. In this paper, we present a new method of edge-based MEEF for analyzing and characterizing MEEF-based hot spots that overcomes the limitations of the traditional cutline approach. Application of the technique to analyze full-field pixel-based two dimensional (2D) MEEF color maps of several different design clips is explained. Process window (PW) is the most important metric in lithography simulations for evaluating the performance of a given RET solution. Traditionally, process window calculation assumes a perfect mask, with no mask errors or corner rounding. In a low k1 regime, MEEF increases enough that mask errors can no longer be ignored in PW evaluation. A method of calculating "MEEF-aware" common process windows and creating a MEEF-aware process variation (PV) band, including mask bias, is presented, and wafer image variability is examined under several process variations, including dose, defocus and mask error. Results of MEEF-aware source-mask optimization (SMO) and design rule exploration using inverse lithography technology (ILT) are also presented.