We present Mask Space Optimization (MSO), an integrated reinforcement learning (RL) engine that automatically tunes complicated multi-domain steps of the inverse lithography technology (ILT) and source-mask optimization (SMO) flow. MSO adaptively explores high-dimensional parameter spaces, orchestrates staged parallel explorations across subspaces, and directly optimizes lithographic quality metrics. Evaluations across DUV and EUV layers show substantial turn-around-time (TAT) reductions and quality-of-result (QoR) improvements, demonstrating the practical benefit of intelligent automation for low k1 lithography challenges.

Upcoming generations of integrated circuits (e.g., below the 14 angstrom device node) will be achieved with the help of anamorphic optics in high-NA EUV scanners. Layers exposed on high-NA anamorphic scanners will require two or more stitched mask exposures to achieve the equivalent exposure area of previous-generation scanners. In this paper we show examples of how simultaneous co-optimization of stitched exposures & masks using ILT can improve resolution, process window, edge-placement error, mask rule check limitations and design rule restrictions of real design patterns in advanced high-NA EUV processes with stitched exposure fields. These results show improvement for the negative effects of double exposure processes in mask manufacturing, main feature wafer pattern fidelity, traditional sub-resolution assist features and stray light reducing sub-resolution grid feature placement. We also describe how co-optimized stitching ILT can help minimize overlay sensitivity via overlay-aware ILT mask co-optimization in the stitch region. We also make comparisons of ILT single exposure and stitched mask optimization to more traditional single-segment solver model-based optical proximity correction for complex stitching logic layouts and corner cases from parametric test patterns.

The lithography industry has historically striven to improve resolution by reducing wavelength and increasing the lens’ numerical aperture (NA). The introduction of 0.33 NA extreme ultraviolet (EUV) lithography into high-volume manufacturing (HVM) represents the largest jump in resolution ever achieved by the industry. However, even this resolution is not sufficient for the patterns required for beyond the 2 nm logic technology node. This is due to low contrast and the diffraction limit of current EUVL scanners for the mask patterns required for these nodes. Instead, the resolution must be improved by increasing the NA. This will also increase the contrast of patterns which had insufficient contrast at 0.33 NA, which will in turn improve LCDU and defectivity. This change is not without its challenges though. Increasing the NA from 0.33 to 0.55 will cause a significant reduction in depth of focus. In addition, stronger mask 3D effects can cause pattern dependent shifts in best focus. As a result, the common overlapping process window of several critical patterns can become strongly diminished. The use of anamorphic optics will require two separate half-field exposures to obtain the equivalent of a single full-field exposure on current EUV and DUV scanners. For some chip sizes, this will require stitching two half-fields together to pattern the full chip area. In previous technology nodes, the process window could be improved using SMO and SRAFs. In addition, over the last five years, the industry has put significant effort into studying alternative absorbing materials. These materials can significantly reduce the mask 3D effects by reducing the thickness of the absorber. The use of alternative absorbers alone will not be sufficient for improving the overlapping process window. Instead, several techniques must be simultaneously utilized in order to ensure sufficient overall process window. Optimization of overlapping process windows is critical for successful insertion of high-NA EUVL into HVM. In this paper we analyze how the process window of critical patterns can be optimized by using different optimizations. We will show for realistic mask designs how process window can be improved in different process steps. Double exposure from half-field stitching will also be included in the process evaluation. We use both rigorous and compact modeling in a complimentary fashion for overall process optimization analysis. All techniques presented in this paper accurately model the anamorphic, centrally obscured optics of the upcoming next-generation high-NA scanners.

For the past few decades, PPA (performance, power, and area) demand of computation infrastructure has been driving exponential increase of chip density. In recent years, the challenges of printability and process window for advanced manufacturing node continuously motivated innovations in reticle enhancement techniques, notably the adoption of inverse lithography technology (ILT) and curvilinear mask. We have observed a few challenges: 1) ILT provides unmatched quality of results but does incur additional computation time to manage; 2) for curvilinear mask, though the benefits are evident, the associated data volume is very large; and 3) mask consistency remains a critical component for design manufacturability. To utilize the advanced RET techniques to their full potential, it is crucial to identify the repeating structures in design layout and reuse the correction result, getting three benefits at the same time: reducing mask preparation runtime, reducing mask data volume, and improving mask consistency. Conventional layout repetition analysis is based on native design hierarchy. However, in many cases, the input layout for mask synthesis flows is either completely stripped of hierarchy or contains sub-optimal hierarchy. Some layout hierarchy can be detected and reconstructed using manual methods such as using user generated pattern library of highly repeating structures in conjunction with pattern matching technology. However, the preparation of such libraries is a formidable effort, and a significant number of repetitions in designs will be overlooked by this approach. In this paper, we investigate the automatic detection of repeating geometry structures and formed a hierarchy that is optimized for mask synthesis. The detection supports any process layer and both Manhattan and all-angle designs. The engine detects repeating regions of arbitrary shape. The detected repeating structures can also be applied within the chip or across chips to accelerate correction to further improve mask consistency. By scaling well to hundreds of processors, the distributed hierarchy extraction is very efficient for a full chip layout. For highly repetitive layouts, mask synthesis runtime reduction of more than an order of magnitude has been observed by performing this hierarchy extraction.

In advanced semiconductor memory manufacturing, the feature size keeps aggressively shrinking, creating problems in the fabrication process and leading to decreasing yield. Three key factors that can impact memory process and yield are lithographic process window, full field CD uniformity (CDU), and correction run time performance. In this paper, we describe and present a mask processing technique utilizing a) global array detect (GAD) for detecting and optimizing cell repetition, b) periodic boundary condition (PBC) for preserving simulation and mask symmetry, and c) cell-level ILT (CLILT) flow to process repeated cell regions and blend various design parts. With GAD + PBC + CL-ILT processing, we can achieve a perfectly consistent mask array region with enlarged process window and minimum local CD variation for a full field mask. Moreover, with fewer pattern units (called templates) to process, we can complete full chip ILT with reasonable time and compute resources compared to OPC full chip correction. In this paper, we show simulation and wafer print results including pattern fidelity, process window, mask consistency, and run time data.

The first high-NA EUVL scanner will have an 0.55 NA and will use anamorphic magnification. Therefore, the standard 10×13 cm lithography mask will be imaged into a 2.6×1.65 cm rectangle on the wafer due to the increased reduction factor of the lens' vertical direction. Layers exposed on high-NA anamorphic scanners will require two stitched halffields to achieve the equivalent exposure area of previous-generation scanners. Stitching strategies will depend on the product type being manufactured. For chips with a large die area, it will be necessary to stitch fields across the die. For smaller chips, it may be advantageous to use three stitched exposures depending on the die size. In any case, the stray light from neighboring fields and black border proximity effects cause challenges for robust manufacturing. Some recent studies have shown that the CD may vary significantly as a function of the proximity to the black border edge due to multilayer stresses. In addition, stitching through a die has increased optical proximity effects which will need to be corrected to achieve the desired wafer CD. In this paper we examine the effects relevant to designing a stitched process, quantify manufacturing tolerances, and show how these effects can be corrected with EDA. More specifically, we examine the optical and mechanical properties of the multi-layer black border etch and optimization of sub-resolution gratings to reduce reflectivity with phase shifting absorber materials. Ultimately, we will show that for a well designed stitch, the effects of stitching can be corrected without impact to process window.

With the introduction of Augmented Reality, Virtual Reality, and Mixed Reality (AR/VR/MR) applications, the fabrication of photonics devices is approaching a high volume manufacturing level. To scale these products to consumer friendly dimensions, there is still significant shrink needed for many not yet available components such as ultrasmall cameras, metalenses, microdisplays, and combiner optics. AR/VR/MR optical components include metalenses patterned over large areas, and the fidelity of these patterns may have a significant impact on performance. In this study, we apply OPC to the design intent and examine the implication of various lithographic and correction techniques on metalens performance through simulation. In addition, we investigate the root causes of the manufacturing process variability and its impact on metalens functionality. These devices are analyzed by comparing light propagation through the simulated manufactured system using rigorous lithographic models to the optimal system based on the design intent. The study finds that the size and shape of meta-atoms have a different impact on optical performance, depending on the type of the metalens.

In this work, we demonstrate our first-principles based methodology to include atomistic level simulations to evaluate the promise of different metals on the performance of MOL/BEOL interconnects. The specific metals that we focus on include Cu, Ru (both fcc and hcp). Co. and Mo where the conductivity of these metals, including the degradation from grain boundaries extracted from ab initio simulations, is included in a parasitic field solver and subsequently used to extract the interconnect parasitics of standard cells. Lithography considerations are addressed through simulations of patterned. "real" wires. PPA is evaluated through simulations of an 128x128 SRAM memory array where we find significant improvement in the read and write delay of 20% and 40%, respectively when we replace M1 with Ru(fcc).

As technology continues to scale aggressively, source mask optimization (SMO) is now a key resolution enhancement technique (RET) to maximize the process window. Synopsys (c) has developed new source mask optimization tool Proteus SMO that demonstrated this improvement. Proteus SMO is equipped with comprehensive functionalities for computing the optimum source and mask. High flexibilities of source types, mask recipes, models, optimizers, and cost functions are provided. For enabling accurate simulation results, integration of Sentaurus Lithography (S-Litho) is also possible when needed. Moreover, the industrial-proven Inverse Lithography Technology (Proteus ILT) mask synthesis is integrated within Proteus SMO further maximizing the process window. Taking advantage of ILT and S-Litho simulation solutions, Proteus SMO could achieve significant lithographic performance improvement. In this paper, Proteus SMO is applied on a DRAM layer with a fixed mask. Comparison of results between Proteus SMO sources with that of the baseline source shows significant improvement in process window over the baseline source both in simulation and on wafer level.

In EUV lithography, the short wavelength and residual mirror surface roughness increase the flare levels across the slit. As a key research point, the flares of different exposure fields are carefully discussed by numerical simulation. To ensure the effectiveness and practicability of our simulations, the test patterns are generated according to the general design rules for 7nm technology node. The NILS, process variation band (PVB) and MEEFs from mask optimizations and source mask optimizations (SMO) results are compared. From the comparisons, the constant flare has a greater influence on NILS and PVB than that on MEEF. In contrast, the flare map caused more reduction on the MEEF values. By using Proteus Workbench, the source maps under different flares conditions are optimized. The simulation results show that flare has direct impact on NILS and PVB, and source optimization is needed to improve depth of focus (DOF) and exposure latitude (EL) to reduce the impact of flare.

Over the last several technology generations the slower feature scaling has been increasingly complemented by DTCO. Initially, DTCO was employed at a smaller scale to decide which technology modules to introduce to achieve target PPAC (Power-Performance-Area-Cost) specs. Then it was extended to evaluate and optimize a combination of design rules and logic library cell design. Now, DTCO is being extended to cover logic block PPAC for a variety of specific target applications ranging from high performance computing to low power mobile chips. In this talk, we focus on the latest trends in logic block level PPAC analysis and highlight several key components of such analysis that are necessary to achieve the required accuracy at the early pre-silicon DTCO stages.

New inverse methods such as model-based SRAF placement, model-based SRAF optimization, and full main + assist feature ILT are well known to have considerable benefits in finding flexible mask pattern solutions to improve process window and CD control. These methods have traditionally relied on compact models that are tuned to match resist measurements at a single z-height or slice. At this slice in the resist, some critical failure modes such as top loss and scumming are not detected. In this paper, we describe and present results for a methodology to extend ILT's process window improvement capabilities, and to co-optimize mask patterns with awareness of the resist profile. These improvements are proven to reduce the risk of patterning failures at the bottom and top of critical resist features, which a typical mask correction process would not alleviate. Ideally, mask optimization would use a full rigorous TCAD resist model to guide the correction at multiple heights in the resist. However, TCAD models are significantly slower than compact models in simulations and ILT already has high computational requirements. Therefore, we have generated compact models which are fitted to the TCAD model resist profile data. We show the significant process window improvements obtained with this new resist 3D aware ILT methodology.

Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitch splitting methodologies. DPT has also been used to improve patterning of certain device layers with k1 values slightly above 0.25, due to the difficulty of achieving sufficient pattern fidelity with only a single exposure. Unfortunately, this broad adoption of DPT also came with a significant increase in patterning process cost. In this paper, we discuss the development of a single patterning technology process using an integrated Inverse Lithography Technology (ILT) flow for mask synthesis. A single pattering technology flow will reduce the manufacturing cost for a k1 > 0.25 full chip random contact layer in a memory device by replacing the more expensive DPT process with ILT flow, while also maintaining good lithographic production quality and manufacturable OPC/RET production metrics.This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.

During early stage development of a DSA process, there are many unknown interactions between design, DSA process, RET, and mask synthesis. The computational resolution of these unknowns can guide development towards a common process space whereby manufacturing success can be evaluated. This paper will demonstrate the use of existing Inverse Lithography Technology (ILT) to co-optimize the multitude of parameters. ILT mask synthesis will be applied to a varied hole design space in combination with a range of DSA model parameters under different illumination and RET conditions. The design will range from 40 nm pitch doublet to random DSA designs with larger pitches, while various effective DSA characteristics of shrink bias and corner smoothing will be assumed for the DSA model during optimization. The co-optimization of these design parameters and process characteristics under different SMO solutions and RET conditions (dark/bright field tones and binary/PSM mask types) will also help to provide a complete process mapping of possible manufacturing options. The lithographic performances for masks within the optimized parameter space will be generated to show a common process space with the highest possibility for success.

In order to achieve an economical design-to-mask (DTM) development cycle in the low k1 domain, designers, lithographers, and mask makers needed to move away from many sequentially isolated developmental activities onto one collaborative environment managed by a computational lithography platform that integrates their respective ecosystems. 1,2 A successful development cycle used to be achievable by designers providing designs to lithographers, who then provided RET/OPC solutions to realize designs, but once k1 fell below a certain level, the lithographers could not provide solutions to realize some critical designs, which then required feedback to designers for further redesigns requiring further lithographic evaluation cycles. So collaboration and automations between lithographers and designers became necessary to reduce feedback loops and development cycle time. RET and design solutions also were impacted by mask making, and so mask maker's feedback on MRC and other constraints needed to be integrated for all three groups to achieve an economical DTM. As many lithographers attempted to print sub-80 nm pitches with 193 nm wavelength, it became necessary to use double patterning to achieve feature resolution. With the effective pitch doubling on each split layer, there could be significant increased design rule freedom for certain complex design situations. Using an integrated computational lithographic platform, one could find design space sweet spots that could further achieve optimal lithographic performance. In this paper, the optimization of design rules (DRD) for double pattern designs (~60 nm pitch) was explored with the mask maker's perspective. The experiment to be presented started with a 2x nm design set of clips. Each set of clips underwent size/width/space/pitch variations to generate a design space, and then each design space underwent SMO with an inverse lithography technology (ILT) engine using various mask MRC's and manhattan segmentations. The lithographic results were analyzed with respect to MRC and manhattan segmentation to show their impact on design space and mask solutions.

Clear-field photo-masks offer significant advantages over dark-field photo-masks for some important classes of target patterns, including small isolated features and dense arrays of contacts. This work compares lithographic performance of clear-field and dark-field images when mask patterns are optimized for respective mask tones. Since the purpose is to study optical behavior, computed images without resist models were compared. In order to explore performance limits, optimized masks were not constrained to limit their complexity. Calculated images were compared for clear-field and dark-field masks, with either opaque or 6% transmission, 180-degree phase-shifted absorbers. In each case, mask patterns were independently optimized to print the targets, which were a set of square and rectangular arrays of contact holes with various dimensions and pitches. The range of the target patterns extended to the limits of ArF resolution with water immersion. Because the intent was to compare inherent optical performance of positive and negative-tone imaging, the study did not use resist models that would combine materials properties or behaviors into the results, but simply applied a constant threshold to calculated intensities to obtain images. Contrast, MEEF, and deviation of images with defocus were the basis of optimizing the mask patterns, and were compared for the four combinations of mask tones and absorbers. Best contrast and MEEF were obtained with bright-field masks that had attenuated, phase-shifting absorbers. The amount of improvement depended on the size of the mask patterns relative to that of their corresponding targets, set here by varying the intensity threshold for the images during mask optimization. Differences in how the images of the four types of masks changed with defocus were statistically insignificant.

A wafer's printed CD error can be impacted by unaccounted mask making process variation. Unaccounted mask CD and/or corner rounding alters the intended drawn mask pattern contributing to a wafer's printed CD error. During OPC wafer calibration, average mask bias and corner rounding are accounted for in the OPC model, but random local mask making process variations or mask-to-mask variations can be difficult to account in such model calibration. Thus when a wafer's CD has error, it can be difficult to determine if the general root cause was due to mask or wafer or both. An in-line monitoring application has been developed to extract accurate mask CD and rendered mask polygon from collected mask CD-SEM images. Technical information will be presented on the challenges of accurately extracting information from SEM images. In particular, discussions include SEM image calibration, contour extraction, inverse pattern rendering, and general image processing to account for mask SEM aberrations (translation, rotation, & dilation), tool-to-tool variation, vendor-to-vendor variation, run-to-run variation, and dark/bright field pattern-to-pattern variation. After accurate mask SEM contours are obtained, lithographic simulations are performed on extracted polygon contours to determine the impact of mask variation on wafer CD. This paper will present detail information about the Inverse Pattern Rendering (IPR) capabilities developed for a virtual Wafer CD (WCD) application and its results, which is proven to achieved 0.5 nm accuracy across multiple critical layers from 28 nm to 40 nm nodes on multiple CD-SEM tools over multiple mask shop locations.

The ITRS roadmap(1) lists double patterning 193 nm immersion exposure with inverse lithography as the likely solution through the 22 nm half pitch generation. Three different patterns, scaled to 56 nm pitch, were explored using inverse lithography.(2,3) The patterns are a trim mask design adapted from Schenker, et al.(4), a bit line design published by Pyo, et al.(5) and a metal layer design published by Lucas, et al.(6). A free form gray scale illuminator was determined for each pattern. Good results were obtained for the trim mask design with a process variation of less than 8 nm for 50 nm of defocus and MEEF less than 6. The bit line design had to be modified from the published version which increased the pattern area by 18.8%. For this pattern there was a maximum process variation of 11 nm for 50 nm of defocus and MEEF less than 14. The metal layer design had to be modified which increased the pattern area by 2.6%. With these changes there was a maximum process variation of 8.4 nm for 50 nm of defocus and MEEF less than 7.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns under mask inspection optical conditions continues to diminish. Furthermore, as mask complexity and MEEF has also increased, it requires detecting even smaller defects in the already narrower pitch mask patterns. This leaves the mask inspection engineer with the option to either purchase a higher resolution mask inspection tool or increase the detector sensitivity on the existing inspection system or maybe even both. In order to meet defect sensitivity requirements in critical features of sub-32nm node designs, increasing sensitivity typically results in increased nuisance (i.e., small sub-specification) defect detection by 5-20X defects making post-inspection defect review non-manufacturable.As a solution for automatically dispositioning the increased number of nuisance and real defects detected at higher inspection sensitivity, Luminescent has successfully extended Inverse Lithography Technology (ILT) and its patented level-set methods to reconstruct the defective mask from its inspection image, and then perform simulated AIMS dispositioning on the reconstructed mask. In this technique, named Lithographic Plane Review (LPR), inspection transmitted and reflected light images of the test (i.e. defect) and reference (i. e., corresponding defect-free) regions are provided to the "inversion" engine which then computes the corresponding test and reference mask patterns. An essential input to this engine is a well calibrated model incorporating inspection tool optics, mask processing and 3D effects, and also the subsequent AIMS tool optics to be able to then simulate the aerial image impact of the defects. This flow is equivalent to doing an actual AIMS tool measurement of every defect detected during mask inspection, while at the same time maintaining inspection at high enough resolution. What makes this product usable in mask volume production is the high degree of accuracy of mask defect reconstruction, predicting actual AIMS measurements to within +/-4% CD error for > 95% of defects while not missing any OOS (out-of-specification) defect and maintaining high simulation throughput of >= 250 defects/min on Luminescent's distributed computing platform. This technique enables inspection recipes to be setup based on the sensitivity required to detect small but lithographically-significant defects, even if in the process a large number of nuisance defects are detected.LPR is being implemented as an integral part of defect classification for high-volume sub-32nm technology nodes and higher. Furthermore, this technique will be essential to the lithographic disposition of defects detected on EUV masks inspected under non-actinic conditions.