The intra-cellular calcium signaling pathways of a neuron depends on both biochemical reactions and diffusions. Some quasi-isolated compartments (e.g., spines) are so small and calcium concentrations are so low that one extra molecule diffusing in by chance can make a nontrivial difference in concentration (percentage-wise). These rare events can affect dynamics discretely in such a way that they cannot be evaluated by a deterministic and continuous simulation. Stochastic models of such a system provide a more detailed understanding of these systems than existing deterministic models because they capture their behavior at a molecular level. Our research focuses on the development of a high performance parallel discrete event simulation environment, Neuron Time Warp (NTW), which is intended for use in the parallel simulation of stochastic reaction-diffusion systems such as intra-calcium signaling. NTW is integrated with NEURON, a simulator which is widely used within the neuroscience community. We simulate two models, a calcium buffer and a calcium wave model. The calcium buffer model is employed in order to verify the correctness and performance of NTW by comparing it to a sequential deterministic simulation in NEURON. We also derived a discrete event calcium wave model from a deterministic model using the stochastic IP3R structure.

Chemical reactions and molecular diffusion in a neuron play an important role in the transmission of signals within a neuron. Discrete event stochastic simulation of the chemical reactions and diffusion provides a more detailed view of the molecular dynamics within a neuron than continuous simulation. As part of the NEURON project we developed a multi-threaded optimistic PDES simulator, Neuron Time Warp-Multi Thread, for these reaction-diffusion models. We used NTW-MT to simulate a calcium wave model due to its importance to the neuroscience community and representativeness of the types of reaction-diffusion problems which need to be solved in neuroscience. During the course of our experiments we observed a decided need for load balancing and window control to achieve large-scale runs. In this paper, we improved the Q-Learning and Simulated Annealing load balancing algorithm according to characteristics of reaction and diffusion model to address both of these issues. We evaluated the algorithms by various parameters in various scales, and our results showed that (1) the algorithm improves the execution time for small simulations by up to 31% (using Q-Learning) and 19% (using SA) and (2) the SA approach is more suitable for larger models, decreasing the execution time by 41%.

Cells exhibit stochastic behavior when the number of molecules is small. Hence a stochastic reaction-diffusion simulator capable of working at scale can provide a more accurate view of molecular dynamics within the cell. This article describes a parallel discrete event simulator, Neuron Time Warp-Multi Thread (NTW-MT), developed for the simulation of reaction diffusion models of neurons. To the best of our knowledge, this is the first parallel discrete event simulator oriented toward stochastic simulation of chemical reactions in a neuron. The simulator was developed as part of the NEURON project. NTW-MT is optimistic and thread based, which attempts to capitalize on multicore architectures used in high performance machines. It makes use of a multilevel queue for the pending event set and a single rollback message in place of individual antimessages to disperse contention and decrease the overhead of processing rollbacks. Global Virtual Time is computed asynchronously both within and among processes to get rid of the overhead for synchronizing threads. Memory usage is managed in order to avoid locking and unlocking when allocating and deallocating memory and to maximize cache locality. We verified our simulator on a calcium buffer model. We examined its performance on a calcium wave model, comparing it to the performance of a process based optimistic simulator and a threaded simulator which uses a single priority queue for each thread. Our multithreaded simulator is shown to achieve superior performance to these simulators. Finally, we demonstrated the scalability of our simulator on a larger Calcium-Induced Calcium Release (CICR) model and a more detailed CICR model.

The intracellular calcium signaling pathways of a neuron consist of biochemical reactions along with molecular diffusion. It is known that stochastic discrete event simulation of these pathways provides a more detailed understanding of the pathways than deterministic simulators because they capture behavior at a molecular level. Our research employs a parallel discrete event simulation simulator, Neuron Time Warp (NTW), which is intended for use for the simulation of neurons. In previous work we built a discrete event Ca 2+ wave model. However, we did not achieve the expected performance because of an imbalance in the computation between the area of the neuron covered by the Ca 2+ wave and the remaining area of the neuron. In this paper we describe a dynamic load balancing algorithm and a dynamic window control algorithm for NTW. We make use of Q-learning to determine the basic parameters of the algorithm. Using this algorithm we obtained an improvement in the performance of the simulator of up to 30%.

Detailed simulation of chemical reactions and the diffusion of ions through a neuronal membrane presents challenges due to the multiple scales at which this occurs, scales that require development and consolidation of a number of different simulation methodologies. In this paper, we describe Neuron Time Warp (NTW), a part of the NEURON project for development of multi-scale tools for simulations of brain parts and brains. NTW relies upon the Next Subvolume Method, a stochastic Monte Carlo algorithm used to simulate chemical reactions within the membrane of a neuron. We make use of a model of a dendrite branch on which to evaluate NTW's performance using MPI and shared memory on a multi-core machine. This work is a first step towards the development of multi-scale simulation models which are capable of portraying the behavior of a neuron with greater fidelity then is possible with differential equation based models alone.

As computing systems grow to exascale levels of performance, the smallest elements of a single processor can greatly affect the entire computer system (e.g. its power consumption). As future generations of processors are developed, simulation at the gate level is necessary to ensure that the necessary target performance benchmarks are met prior to fabrication. The most common simulation tools available today utilize either a single node or small clusters and as such create a bottleneck in the development process. This paper focuses on the massively parallel simulation of logic gate circuit models using supercomputer systems. The focus of this performance study leverages the OpenSPARC T2 processor design using Rensselaer's Optimistic Simulation System (ROSS). We conduct simulations of the crossbar component on both a 24-core SMP machine and an IBM Blue Gene/L. Using a single SMP core as the baseline, our performance experiments on 1024 cores of the Blue Gene/L demonstrate more than 131-times faster execution. Our results capitalize on the balanced compute and network power of the Blue Gene/L system.

In this paper, we describe a distributed dynamic load balancing algorithm for parallel optimistic gate level simulation. Our optimistic simulator is based on Time Warp. The load balancing algorithm makes decisions based on the processing and communication loads at each processor. At the core of the algorithm is a genetic algorithm which is used to determine the values of the tuning parameters associated with the algorithm. It also determines the size of the time window of the simulator. The time window is a mechanism used to control the level of optimism of an optimistic simulator in order to avoid excessive rollbacks. An important feature of the genetic algorithm is that it is on-line, i.e. it is executed during the course of the simulation. The genetic algorithm is executed in one processor while the other processors execute the simulation and the load balancing algorithm. Experimental results have indicated a significant decrease in the execution time of the simulationup to a 70% decrease in the simulation time of an optimistic simulator.

A major part of the design process for Integrated Circuits (IC) is the process of circuit verification, in which the correctness of a circuit's design is evaluated. Discrete event simulation is a central tool in this effort. As proscribed by Moore's law, the number of transistors which can be placed on an IC doubles every 18 months. As a result, simulation has become the major bottleneck in the circuit design process. To alleviate this difficulty, it is possible to make use of parallel (or distributed) circuit simulation. In this paper, we make use of a parallel gate-level simulator which we developed and which is based upon Time Warp. Gate-level simulations exhibit two characteristics which can easily result in either instability or severely degraded simulation performance. Because of the low computational granularity of a gate-level simulation and because the computational load varies throughout the course of the simulation, the performance of Time Warp can be either severely degraded or be unstable. Restraining the optimism of Time Warp via a bounded window and utilizing dynamic load balancing are approaches to deal with these difficulties. In this paper, we make use of learning techniques from artificial intelligence (multiagent Q-learning, simulated annealing) to develop a combined bounded window and dynamic load balancing algorithm for parallel digital logic simulation. We evaluated the performance of these algorithms on open source Sparc and Leon designs and on two Viterbi decoder designs. We observed up to 60 percent improvement in simulation time of one of the decoders using this approach.

Numerical simulation of gravitational N-body systems is an important tool for studying the dynamic behaviour of stellar systems, and in some cases is the only option available given the extremely large time scales involved. The direct summation approach, which evaluates the force between each pair of particles at each time step, produces the most accurate results. However despite many algorithmic advances this method remains a computationally challenging problem owing to its O(N-2) scaling characteristics. The desire to model increasingly larger systems has spurred the adoption of parallel computation techniques, but unfortunately many of the strategies used to accelerate sequential direct N-body simulations hinder their efficient parallelization. This paper investigates the use of parallel discrete event simulation as an alternative to the usual iterative time-stepping approach. By decomposing typical operations into finer-grained events, it is shown that there exists considerable potential for exploiting the model's inherent concurrency. In addition, it is demonstrated how certain optimizations that are normally difficult to parallelize are incorporated naturally into the parallel discrete event paradigm.

Parallel discrete event simulation can be applied as a fast and cost effective approach for the gate level simulation of current VLSI circuits. In this paper we combine a dynamic load balancing algorithm and a bounded window algorithm for optimistic gate level simulation. The bounded time window prevents the simulation from being too optimistic and from excessive rollbacks. We utilize a machine learning algorithm (Qlearning) to effect this combination. We introduce two dynamic load-balancing algorithms for balancing the communication and computational load and use two learning agents to combine these algorithms. One learning agent combines the two learning algorithms and learns their corresponding parameters, while the second optimizes the value of the time window. Experimental results show up to a 46% improvement in the simulation time using this combined algorithm for several open source circuits. To the best of our knowledge, this is the first time that Q-learning has been used to optimize an optimistic gate level simulation.

In this paper, we present a dynamic load-balancing algorithm for parallel digital logic simulation making use of reinforcement learning We first introduce two dynamic load-balancing algorithms oriented towards balancing the computational and communication load respectively and then utilize reinforcement learning to create an algorithm which is a combination of the first two algorithms In addition, the algorithm determines the value of two important parameters the number of processors which participate in the algorithm and the load which is exchanged during its execution. We investigate the algorithms on gate level simulations of several open source VLSI circuits

According to Moore's law the complexity of VLSI circuits has doubled approximately every two years, resulting in simulation becoming the major bottleneck in the circuit design process. Parallel and distributed simulations can be applied as fast, cost effective approaches to the simulation of large, complex circuits. In this paper, a simple yet effective simulated annealing-based approach is proposed to optimize the choice of a time window for optimistic parallel simulation. We chose gate level circuits simulations as our experimental vehicle. Our results show up to a 52% improvement in the simulation time using our simulated annealing algorithm. To the best of our knowledge, this is the first time that SA has been applied to optimize the performance of time warp simulations.

In this paper, we present a dynamic load-balancing algorithm for optimistic gate level simulation making use of a machine learning approach. We first introduce two dynamic load-balancing algorithms oriented towards balancing the computational and communication load respectively in a Time Warp simulator. In addition, we utilize a multi- state Q-learning approach to create an algorithm which is a combination of the first two algorithms. The Q-learning algorithm determines the value of three important parameters- the number of processors which participate in the algorithm, the load which is exchanged during its execution and the type of load-balancing algorithm. We investigate the algorithm on gate level simulations of several open source VLSI circuits.

As proscribed by Moore's law, the size of integrated circuits has grown geometrically, resulting in simulation becoming the major bottleneck in the circuit design process. Parallel simulation provides us with a way to cope with this growth. In this paper, we describe an optimistic (time warp) parallel discrete event simulator which can simulate all synthesizeable Verilog circuits. We investigate its scalability and describe a machine learning based dynamic load balancing algorithm for use with the simulator. We initially developed two dynamic load balancing algorithms to balance the load and the communication, respectively, during the course of a simulation. Making use of reinforcement learning (RL), we then created an algorithm which is an amalgam of these two algorithms. To the best of our knowledge, this is the first time that RL has been used for the dynamic load-balancing of time warp. We investigated the scalability and the effectiveness of the dynamic load balancing algorithms on gate level simulations of several realistic very large scale integration (VLSI) circuits. Our experimental results showed that our simulator is indeed scalable. They also reveled a 88.6% improvement in the simulation time through the use of our RL algorithm.

It is well known that controlling the optimism in Time Warp is central to its success. To date, this problem has been approached by constructing a heuristic model of Time Warp's behavior and optimizing the models' performance. The extent to which the model actually reflects reality is therefore central to its ability to control Time Warp's behavior. In contrast to those approaches, using genetic algorithms avoids the need to construct models of Time Warp's behavior. We demonstrate, in this paper, how the choice of a time window for Time Warp can be transformed into a search problem, and how a genetic algorithm can be utilized to search for the optimal value of the window. An important quality of genetic algorithms is that they can start a search with a random choice for the values of the parameter(s) which they are trying to optimize and produce high quality solutions.

As a consequence of Moore’s law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. On the other hand, parallel or distributed simulations can be applied as fast, feasible and cost effective approaches for correctness analysis of current VLSI circuits. In this paper, we developed the first Time Warp simulator which can simulate in parallel all synthesizable Verilog circuits. We observed 4,000,000 events per second on 32 processors for the Viterbi decoder with 800k gates. We also observed that the load of different processors differ by up to 12M events during the course of the simulation. As a result, we first develop two new dynamic load balancing approach which balance the load during the simulation. Afterward, we utilize reinforcement learning to create an algorithm which is a combination of the first two algorithms. We investigate the algorithms on gate level simulations of several open source VLSI circuits. Our results show up to a 25% improvement in the simulation time using the reinforcement learning algorithm. To the best of our knowledge, this is the first time that reinforcement learning has been used for the dynamic load-balancing of Time Warp.

Parallel discrete event simulation has been established as a technique which has great potential to speed up the execution of gate level circuit simulation. A fundamental problem posed by a parallel environment is the decision of whether it is best to simulate a particular circuit sequentially or on a parallel platform. Furthermore, in the event that a circuit should be simulated on a parallel platform, it is necessary to decide how many computing nodes should be used on the given platform. In this paper we propose a machine learning algorithm as an aid in making these decisions. The algorithm is based on the well-known K-Nearest Neighbor algorithm. After an extensive training regime, it was shown to make a correct prediction 99% of the time on whether to use a parallel or sequential simulator. The predicted number of nodes to use on a parallel platform was shown to produce an average execution time which was not more than 12% of the smallest execution time. The configuration which resulted in the minimal execution time was picked 61% of the time.

As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. In this paper, we examine the performance of a parallel Verilog simulator on large, real designs. As previous work has made use of either relatively small benchmarks or synthetic circuits, the use of these circuits is far more realistic. We develop a parser for Verilog files enabling us to simulate in parallel all synthesizable Verilog circuits. We utilize four circuits as our test benches; the LEON Processor, the OpenSparc T2 processor and two Viterbi decoder circuits. We observed 4,000,000 events per second on 32 processors for the Viterbi decoder with 800k gates. A dynamic load balancing approach is also developed which uses a combination of centralized and distributed control in order to accommodate its use for large circuits.

In a Time-Warp-based distributed simulation system, a simulation process must save its states and events to handle rollbacks. Periodically, the global minimum of the timestamps of events and messages in the entire system is calculated. This value is known as the global virtual time (GVT), and it plays an important role in a Time Warp system. GVT is only computed periodically because of the computation overhead. An important problem is to determine the optimal interval between two GVT computations. In this paper we present a new approach that uses a simple Reinforcement Learning technique to select the optimal GVT interval. Used in a Time-Warp-based distributed VLSI simulation system, our method was successful in selecting good GVT interval and improving the system's performance.