Bulk crystal defects are accessible for investigation when silicon crystals are sliced and the defects occur close to or at the surface of wafers. Such near-surface defects can then be delineated by modifying some processes used for preparing clean, polished wafers. The delineated defects usually occur as pits the shape of which depends on the delineation process used. The different shapes of the pits has consequences for their detection by light scattering techniques (laser scanners or surface inspection systems). The density of the such generated surface defects is related to the defect density in the crystal bulk and is influenced by the growth parameters. These surface defects therefore provide a means for studying and for characterizing the bulk defect density.

Based on Fourier transform infrared (FTIR) spectroscopy and bulk micro-defect investigations, in relation to earlier results of other groups, we suggest the following model for oxide precipitate nucleation in N-doped silicon. Around 600 degrees C a nucleation maximum exists where oxide precipitates are formed via oxygen attachment to both NOO and NNO complexes. These complexes are formed by the reaction of NN with interstitial oxygen. Vacancy supersaturation enhances this type of precipitate nucleation. A second nucleation maximum exists around 900 degrees C. This is assumed to be due to a vacancy assisted oxynitride SiOxNy based nucleation process. The higher density of the oxynitride phase compared to silicon oxide and a higher residual vacancy concentration would explain the observed shift of the maximum nucleation rate to higher temperatures around 900 degrees C. (c) 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nitrogen doping of CZ silicon results in an early formation of large precipitate nuclei during crystal cooling, which are stable at 900°C. These are prone to develop stacking faults and high densities of defects inside defect denuded zones of CZ silicon wafers. Simultaneous doping of FZ silicon with nitrogen and oxygen results in two main stages of precipitate nucleation during crystal cooling, an enhanced nucleation around 800°C, which is nitrogen induced, and a second enhancement around 600°C, which depends on the concentration of residual oxygen on interstitial sites. A combined technique of ramping with 1K/min from 500-1000°C with a final anneal at 1000°C for 2h and lateral BMD measurement by SIRM provides a possibility to delineate v/G on nitrogen-doped silicon wafers. Surface segregation of nitrogen and oxygen during out-diffusion can explain the enhanced BMD formation in about 105m depth and the suppressed BMD formation in about 405m depth below the surface. The precipitate growth is enhanced in regions where nitrogen is filled up again after a preceding out-diffusion.

Float zone crystals without nitrogen (N) and with increasing axial nitrogen doping have been grown. Vacancy agglomerates have been delineated in FZ wafers in the low nitrogen doping level with various measurement techniques like flow pattern defects, localized light scattering defects and A- and B-mode failures in MOS capacitors. All these measurement methods revealed vacancy-related defects within equal or smaller than around 0.6 wafer radius dependent on the nitrogen doping. At the transition to vanishing extrinsic defects with higher N doping it was observed that extrinsic gate oxide failures have already disappeared when flow pattern defects (FPDs) and crystal-originated particles (COPs) are still present. From the vacancy concentration in this transition region a high void density and a small void size in fast cooled FZ can be calculated. From this a minimum vacancy concentration and a minimum void size detrimental for gate oxide integrity can be estimated. These small void defects in FZ Si can be eliminated by a sacrificial oxidation leading to injection of Si interstitials.

Breakdown characteristics of MOS capacitors on silicon with nitrogen doping levels up to 2.10(15) at/cm(3) have been analyzed. A high extrinsic defect density was observed for thick (t(OX) = 25 nm) gate oxides. The crystal-originated particle related breakdown for wafers without nitrogen shifted to numerous failures with lower charge-to-breakdown and low electrical breakdown fields with increasing nitrogen level in stepped current ramp stress measurements. Nitrogen doping level was discernible also in the defect density extracted from Weibull plots. Also, in thin gate oxides (t(OX) = 5nm) nitrogen doped samples revealed a high extrinsic defect density. This is in contrast to results that COPs have no detrimental impact onto thin gate oxide integrity.

A novel non-destructive and non-contacting technique for the spatially resolved detection of small leakage currents in electronic devices and MOS materials is presented. Highly-sensitive lock-in infrared (IR-) thermography is used to localize leakage current induced temperature variations down to 10 μK at a lateral resolution down to 5 μm. Leakage currents of about 1 mA can be localized within seconds and some μA may be detected after less than 1 h measurement.

Si(113) may be a competitive substrate material for Si integrated circuits. High-quality SiO2/Si(113) films can be produced by standard oxidation techniques. Based on investigations of the initial stages of oxidation by Scanning Tunneling Microscopy and ab initio calculations, we interpret this result as an effect of tensile stress and reduced diffusivity of oxidation by-products on Si(113). Breakdown behavior (field and charge-to-breakdown) of 5 nm thick oxide layers on Si(113) is better than on Si(001), at least by a factor 2 for charge to breakdown. To evaluate the technological potential of Si(113), gate-controlled diodes were prepared on Si(113) and Si(001) under conditions optimized for Si(001). Electrical measurements demonstrate no significant differences in the density of rechargeable interface states, threshold voltages, and charge carrier generation and recombination. We believe that optimization of the preparation conditions may lead to extremely reliable thin gate oxides on Si(113).

The temperature and shear strain rate dependence of the upper yield point of a few kinds of large diameter silicon crystals was studied. Crucial material attributes, such as doping level, initial oxygen content, and the state of oxygen aggregation after thermal treatment, were taken into account. Overall experimental results show that the deformation behavior of the materials studied here is similar; there is no difference observed between high and low boron-doped 200-mm-diameter and 300-mm-diameter silicon crystals. Further, the right choice of sample orientation and shear strain rate used in experiments have been proved to be significant for the characterization of mechanical strength of silicon wafers subjected to process load. Very low strain rates and forces lying in crystallographic 〈110〉 directions generate local regions of plastic flow caused by an extremely low yield stress. The results allow the optimization of critical high temperature processes used for materials technology and device fabrication.

Yield and reliability of MOS devices are strongly affected by crystal-originated particles which may generate gate oxide integrity (GOI) defects. For the semiconductor industry it is highly desirable not only to measure the density, but also to image the lateral distribution of GOI-defects. A novel technique to image GOI defects across large gate areas has been developed. First, a low-ohmic bias pulse is used to break down nearly all GOI defects in a large-area MOS structure. Then a periodic bias of typically 2V is applied and the local temperature variation caused by the leakage current through the broken GOI defects is imaged by lock-in IR-thermography. This technique has been used to image the GOI defect distribution across 8′′ Czochralski wafers. Various lateral variations of the defect distribution have been confirmed.

Grown-in crystal defects like crystal originated particles (COPs) in Czochralski grown silicon wafers deteriorate the yield of metal oxide semiconductor devices by causing dielectric breakdown of the insulating oxide layer. The technique of lock-in IR-thermography is presented, which allows the localization of active gate oxide integrity (GOI) defects with a lateral resolution of about 10 μm as well as to make a full wafer image of electrically broken down GOI defects. Using this technique, the density and the distribution of GOI defects was determined across whole wafers. MOS structures with Si substrate materials with different COP densities and with various oxide thickness were analyzed. Single GOI defects were activated by a current limited breakdown and localized with lock-in IR-thermography. Planar TEM specimens were prepared and the defect origin was examined.

Epitaxial wafer provide optimal choice for 300 mm advanced wafer requirements in particular with respect to low levels of Crystal Originated Particle (COP) and Localized Light Scatterer (LLS) as well as with respect to cost issues. Due to the specific process flow for 300 mm wafers including double side polishing, all kinds of backside layer treatments are preferably omitted in general, and consequently 300 mm has basically to rely on intrinsic gettering. 300 mm epi pp- wafers were found to show similar gettering capability as compared to polished p- wafers after 0.18 mum thermal CMOS process simulation. For oxygen concentrations of 6x10(17)/cm(3) and below precipitation is negligible and Bulk Micro Defect (BMD) densities are vanishing for polished as well as for epitaxial pp-wafers. Additional thermal pretreatment of Rapid Thermal Annealing (RTA) followed by a nucleation step of 750 degreesC for 5 hours prior to the epitaxial deposition enhances precipitation in this oxygen regime while no precipitation at ail is found for just an RTA step. Precipitation and BMD densities in the oxygen range of 5-6x10(17)/cm(3) can also be obtained by additional co-doping of the epi substrates by nitrogen, being the more cost efficient approach to enhance gettering capabilities. Nitrogen doping also reduces the size of the grown-in defects, COP sizes of 50 nm were found on 300 mm wafers. This allows for rather thin epitaxial layers to efficiently cover substrate related features.

The gate oxide integrity of metal-oxide silicon capacitors has been investigated as a function of gate oxide thickness in the 5 - 10nm range. In this thickness regime the transition takes place from crystal originated particle (COP) failures for thick to nearly COP free intrinsic failures for thin oxides. There are hints that the transition depends on COP size and shape. At the transition the charge-to breakdown range of COP related failures is significantly broadened compared to thicker gate oxides. Furthermore the I-V characteristics of capacitors with a thin oxide showed pronounced current oscillations. Thin gate oxides revealed an increased direct tunneling current and therefore a strong sensitivity to thickness variations also for 5nm gate oxides.