The foundry industry and academia are confronting the limits of Moore’s Law scaling for logic transistors. Silicon field‑effect transistors (FETs) now rely on gate‑all‑around structures and ultrathin channels, even at the cost of decreased carrier mobility and complex fabrication processes. Two‑dimensional (2D) semiconductors offer a promising alternative because they retain their crystalline quality at atomic thicknesses. Nonetheless, whether they truly exhibit higher performance than silicon remains questionable. Here, by implementing a dual‑gate structure on bilayer MoS2 FETs, we mitigate the fringing‑field barrier created by the elevated top contact and achieve high carrier densities without increasing fabrication complexity. Simulations and statistical analysis confirm that the dual‑gate compensates the fringe field, enabling a drain current of 1.55 mA µm−1 even with conventional gold contacts. Quantum‑transport simulation indicates that, with further gate‑length and equivalent‑oxide‑thickness scaling, the on-state current can reach levels comparable to silicon FETs at the 3-nm node, and monolithic 3D integration can extend the applicability of dual‑gate 2D transistors to future logic technologies. A dual-gate structure in bilayer MoS2 FETs is reported, allowing a high carrier density by compensating for the fringing field, which holds promise for 2D semiconductor logic applications.

Kinetic description of carrier transport & trapping across a charge trap layer (CTL) is essential for the accurate modeling of 3D-NAND charge-trap flash devices. In many conventional studies, the immediate thermalization and trapping is assumed, which result in the over-estimation of programming speed. To tackle this issue, several approaches have been proposed to reflect the energy-dependent capture probability of the tunneling-injected carrier. However, there were limitations in improving the predictability of programming behavior in the high-kinetic-energy regime. Through in-depth CTF modeling studies, we could find out that it is important to accurately trace the energy loss of electron through inelastic scattering across CTL for the accurate fitting across the entire bias region. Our new model demonstrates superior calibration capability compared to the conventional approaches without modifying material parameter depending on program voltage. The overestimation of trapped charges in conventional approaches is mainly caused by the uncaptured electrons having highenergy injected over high thermal barrier in multiphonon emission theory. Our model mitigates well programming slope overestimation and removes unphysical behavior observed in the injection-energy-independent relaxation model, which deepens the understanding of charge trapping dynamics and improves the predictability for process optimization for next-generation NAND flash technologies.

In nanoscale transistors, quantum mechanical effects such as tunneling and quantization significantly influence device characteristics. However, large-scale quantum transport simulation remains a challenging field, making it difficult to account for quantum mechanical effects arising from the complex device geometries. Here, based on large-scale quantum transport simulations, we demonstrate that quantum geometrical effects in stacked nanosheet GAAFETs significantly impact carrier injection characteristics. Discontinuities in confinement energy at the constriction-the junction between the bulk source/drain and nanosheet channel-cause substantial carrier backscattering. This degradation becomes more severe as electrons experience higher effective energy barriers, and is further exacerbated at lower scattering rate, lower doping concentrations, and near Schottky barriers where electron depletion regions form. Considering these quantum mechanical bottlenecks, proper device optimization for future technology nodes requires a full quantum-based device structure design at the large-scale level, which enables unique optimization strategies beyond conventional classical prediction.

P. W. Anderson introduced a negative-U (i.e., attractive electron-electron interaction) to describe the scarcity of singly occupied spin states in amorphous materials. To uncover the underlying chemistry behind this phenomenon, we combined structural sampling with quantum-chemical analysis of amorphous silicon nitride (a-SiNx) based on DFT. Our analysis demonstrates that coordination defects act as charge traps, with a density on the order of 1021 per cubic centimeter. These defects render singly occupied electronic states energetically less favorable than paired or fully emptied states, primarily due to electron donor-acceptor interactions. Furthermore, excess charge trapping occurs through chemical bond reorganization, which disrupts the balance of existing electron and hole traps. In addition, we found that in Si-rich a-SiNx, various Si─Si bonding networks exhibit power-law-like size distribution, where larger networks are associated with deeper trap levels. These findings explain why a-SiNx has been used as a charge storage layer in the charge trap flash memory.

The foundry industry and academia dedicated to advancing logic transistors are encountering significant challenges in extending Moore's Law. In the industry, silicon (Si)-based transistors are currently adopting gate-all-around (GAA) structures and reducing channel thickness, even at the cost of decreased mobility, for maximizing gate controllability. To compensate for the reduced mobility, multi-channel structures are essential, making the fabrication process extremely challenging. Meanwhile, two-dimensional (2D) semiconductors are emerging as strong alternatives for the channel material in logic transistors, thanks to their ability to maintain crystallinity even when extremely thin. In the case of 2D semiconductors, introducing a dual gate structure, which has a much lower fabrication complexity, can achieve effects similar to GAA. Through this research, we have identified the fringing field originating from the common structure of elevated top contact in 2D FETs results in a high charge injection barrier. Through simulation and statistical analysis with large-area FET arrays, we confirmed that introducing a dual-gate structure in bilayer MoS2 FETs effectively compensates for the fringing field. We have confirmed that this leads to a significant boost in on-current. Remarkably, even with conventional contacts and polycrystalline materials, we observed a record-high on-current of 1.55 mA/µm. Additional circuit simulations have confirmed the potential for dual gate bilayer FETs to surpass the performance of Si GAAFETs when possessing a gate length of 5 nm, achievable only with 2D materials. Therefore, here we propose that by using 2D materials, we can focus on extreme gate length scaling and monolithic 3D integration rather than the challenging GAA process for extending Moore’s Law.

This study reports the practical limit on contact resistance of Si (1 0 0)/TiSi2 system. The maximum transmission in silicide contact is estimated via the overlap of conducting modes. This ideal limit is then compared versus the coherent transport calculation, where DFT-NEGF is applied to a pool of model interfaces. It is shown that interface scattering increases the contact resistance by an order of magnitude. The barrier tunneling strongly depends on surface termination and coordination defects. For the studied samples, the trend of contact resistance matches the inverse of transmission at Fermi level.

Despite the widespread use of charge-trap flash (CTF) memory, the atomistic mechanism behind the exceptionally stable charge storage at the localized trap sites is still controversial. Herein, by combining first-principles calculations and orbital interaction analysis, a charge-dependent switchable chemical-bond reorganization is elucidated as the underpinning chemistry in the working mechanism of CTF. Especially, positively charged fourfold-coordinated nitrogen (dubbed N+ center), unappreciated until now, is the decisive component of the entire process; once an electron occupies this site, the N+ center disappears by breaking one N─Si bond, simultaneously forming a new Si─Si bond with a nearby Si atom which, in turn, creates fivefold coordinated Si. As a result, the electron is stored in a multi-center orbital belonging to multiple atoms including the newly formed Si─Si bond. It is also observed that hole trapping accompanies the creation of an N+ center by forming a new N─Si bond, which represents the reverse process. To further support and validate this model by means of core-level calculations, it is also shown that an N+ center's 1s core level is 1.0-2.5 eV deeper in energy than those of the threefold coordinated N atoms, in harmony with experimental X-ray photoelectron spectroscopy data.

This paper reports on a novel approach to improve and optimize an output resistance (Rout) which is critical to a long-channel analog MOSFET. The Rout degraded by halo doping can be overcompensated by the slit well inserted along the channel center, reaching the target value of 10Mohm*µm at the channel length of 0.5µm. This improvement is brought by the pinch-off generation at the channel center which makes the drain-side half channel act as a buffer layer for the source-side half channel potential against the drain voltage. The increased fitting parameters can be precisely regressed and optimized by the machine-learning based TCAD scheme, maximizing the overall electrical performance including the Rout.

A rigorous expression for the critical length of backscattering ( $\text{L}_{\textbf {Crit}}$ ) is reported. In the new model, $\text{L}_{\textbf {Crit}}$ is obtained from a weighted sum over the transport domain. It is shown that anisotropy of mean free path (MFP) tunes the profile of weight function. Under equilibrium condition with isotropic MFP, the weight is a uniform distribution. As the field grows, it builds up the anisotropy and confines the weight function around the injection boundary. This process quantifies the transition of $\text{L}_{\textbf {Crit}}$ from low to high field regime. We implemented this model in the non-equilibrium Green’s function (NEGF) solver and investigate the compact model form. Contrary to standard model, it is found that MFP of backscattering ( $\boldsymbol {\lambda } $ ) elongates in high drain-source (Vds) bias. Based on these findings, an update of compact model is proposed and verified.

Recently, the main issue for developing the latest small pixels is maintaining the full-well capacity (FWC) while minimizing image lag as the pixel pitch is scaled down within the sub-micron scale. In this letter, the FWC and image lag characteristics are optimized by varying the photodiode (PD) doping profiles in $0.5~\mu \text{m}$ CMOS image sensors with vertical transfer gates (VTGs) for the first time. Measurements and simulated results of various pitch generations are correlated to propose the most desirable PD doping conditions for $0.5~\mu \text{m}$ pixels which have not been developed yet. As a result, the ceiling position of the top PD doping significantly affects the image lag characteristics resulting in the lowest image lag when increasing the ceiling by 30% from the initial position. In conclusion, a fruitful guideline for photodiode design in 3D active pixel sensors is provided for optimization of FWC and image lag in $0.5~\mu \text{m}$ pixel pitches. Also, this methodology associating potential curve analysis can be of potential use for development in ultra-small pixel pitches in the near future.

Recently dual vertical transfer gates (VTGs), used in sub-micron pixels with full-depth deep-trench isolation (FDTI), have demonstrated superior performance in CMOS image sensors such as improvement of full well capacity (FWC) and charge transfer, as compared to a single VTG. In this work, we investigate characteristics of both pixel schemes based on two design examples, which is carried out using extensive 3D TCAD simulation and automated multi-objective optimization flow with various photodiode implantation conditions satisfying certain design specifications. Simulation results reveal that dual VTGs better control electrostatic potentials along the charge transfer path like a 3D fin-shaped transistor. The enhanced gate controllability also makes the VTG off potential insensitive to the nearby doping concentrations, which is not the case for the single VTG pixel, and thus provides more room for boosting FWC in the photodiode design according to the Pareto front analysis.

The transfer characteristics of the three different CMOS image sensor (CIS) pixel schemes; the vertical transfer gate (VTG) with the front-side deep trench isolation (FDTI), the VTG with the back-side deep trench isolation (BDTI), and the planar transfer gate (PTG) with the BDTI are rigorously studied with 3D TCAD simulation. The electrical potential profiles of photo-diode (PD) region are optimized in terms of full well capacity (FWC) and transfer characteristics for each scheme. The simulated blooming margin potentials are well matched to the experimental blooming signal. According to our TCAD analysis, the VTG with the FDTI scheme showed high full FWC characteristics compared to the PTG with the BDTI and the VTG with the BDTI.

In this paper, circuit benchmark of negative capacitance FinFET (NC-FinFET) are conducted using the in-house TCAD based on 7-nm and 14-nm FinFET technologies with high-κ dielectric replaced by ferroelectric material. The compact model is calibrated accordingly for circuit simulations. Compared with reference FinFET, NC-FinFET enables IOFF reduction and DIBL/SS/ION enhancements. The results of ring oscillator (RO) analysis using the calibrated compact model suggest that 1) the ferroelectric (FE) dipole switching dynamics has negligible impact on the RO delay with the reported FE parameters, and 2) the NC-FinFET-based RO enables energy saving via VDD scaling at a fixed propagation delay. Finally, the impact of FE variability on transistor and circuit metrics is analyzed and found to be insignificant compared to other FinFET variation sources

As the unit pixel size of CMOS image sensors (CISs) decreases to sub-micrometer scale, it has become a controversial issue that an increase of resolution without enlargement of chip size leads to an improvement of image quality. In this study, we introduce a novel image simulation methodology to predict the image quality of CISs with sub-micrometer scale pixels. We predict modulation transfer function (MTF) and signal-to-noise (SNR) trends of the Tetracell CISs when the pixel size decreases from 0.8 to 0.4 μm. In results, MTF of the Tetracell CISs shows an improvement until the pitch of 0.45 μm. The reason of this trend is discussed together with the degeneration of color crosstalk and SNR.

With the aggressive scaling of MOSFET devices below 3nm, the role of TCAD in selecting a feasible device architecture for next node has become extremely important. There is an enormous opportunity cost for each choice, so the pros and cons of each option must be identified through seamless pre-validation using TCAD. Therefore, it is important to understand which TCAD solutions are necessary to validate the architecture candidate in rigorous way. This paper describes which TCAD solutions are important in atomic/device/standard cell/block-chip level for next generation logic pathfinding from the perspective view of a semiconductor manufacturing industry.

An automatic optimization methodology based on AI algorithm is proposed to achieve multi-targeting of various devices in 0.13 μm next BCD process development. The optimized process conditions are simultaneously provided with satisfying various ET-specs of the BCD devices from our method and TCAD analysis. The method has practically been applied to well ion implantation processes shared with seven different devices, and its targeting rate of 87% has been verified through silicon evaluation. Its turnaround time (TAT) is reduced by 90% compared to conventional procedure.

We discuss device models employed in the drift-diffusion simulation of MOSFET transistors at deep cryogenic temperatures. We report potential issues of the commonly used models (the Philips unified mobility model, the high field saturation model, the incomplete ionization model, and the quantization model) at low temperatures and how to resolve the issues. In addition, we present a band tail model to capture the subthreshold slope saturation at low temperatures. We also discuss how to obtain the initial solution and perform the bias ramping to avoid convergence issues. As an application, we study the temperature-dependent operation of a gate-all-around transistor down to 4 K.

A novel algorithm is introduced to extract the electrical roughness at the first principle level. The autocorrelation and root-mean-squared height of roughness spectrum are extracted for 3×3 nm2 Si/SiO2 samples. As an application, the impact of Ge-O bond on electrical roughness is demonstrated. The result concludes that electrical roughness of a given interface can be substantially larger than geometrical values.

The intrinsic limit on ballisticity of ultra-scaled transistors is investigated. A novel probing technique is presented, which locally resolves the loss of incident fluxes. This projection reveals the scalable and unscalable components of reflection. The poor ballisticity is explained by non-equilibrium distribution around the potential barrier, which triggers a substantial unscalable reflections.

It has been proven that the multigrid method is promissing on large-scale scientific simulations. However there still remains some difficulties on applying the multigrid method, which is the system of systems such as FEM on stress analysis or coupled PDEs. Above all, the drift-diffusion model widely used in the device modeling is a typical case belonging to the problems. Because the model has a tight coupling between the electrostatic field and the carrier movements and this property prevents the multigrid method from working effectively. In this paper, we propose a technique to apply the multigrid method to the drift-diffusion model. The technique consists of reflection process between systems coupled in the equation. Consequently the technique helps to solve large-scale device simulations. We show the case of power devices.