This paper proposes a corner analysis approach for CMOS circuits taking into the account radiation effects. The presented simulation approach is implemented using the open-source design automation (EDA) software QUCS-S 25.2.0 and Ngspice 45. It was developed a radiation-sensitive field-effect transistor (RADFET) SPICE macromodel representing threshold voltage shift versus radiation dose. The extraction procedure for this model is based on statistical measurements of pMOS transistors and process corner models (Slow, Typical, Fast) and involves percentile analysis. The article proposes an original design of the RADFET-based radiation sensor with RADFET device and CMOS readout circuit placed on the same die, which allows us to simplify the dosimeter schematic. The sensor output parameter dependency on process parameters, supply voltage, and temperature was investigated using the proposed simulation approach.

This research presents an improved version of the Jiles-Atherton (J.-A.) ferromagnetic core model. The presented model eliminates the distortion of minor hysteresis loops and achieves better matching with measured data for minor loops-a well-known weak point of the unmodified J.-A. model. The proposed J.-A. model extension is backward compatible with the basic model version and requires two or four additional parameters. In addition to providing model equations, this paper considers the practical implementation of the improved J.-A. model using SPICE circuit simulation tools. The developed modular SPICE macromodel set is compatible with both open-source and proprietary circuit simulation software, and it allows for the construction of transformer schematics of any complexity. The proposed model shows a good match with measurement results for hysteresis loops and transient waveforms in transformer circuits.

XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for any active or passive RF or microwave schematic (including microwave monolithic integrated circuits—MMICs) involving transmission lines. The presented models could be used with any circuit simulation backend supporting XSPICE extensions and could be integrated without patching the core simulator code. The presented XSPICE models for microstrip lines take into account the frequency dependency of characteristic impedance and dispersion. The models were designed using open-source circuit simulation software. This study provides a practical example of the low-noise RF amplifier (LNA) design with Ngspice simulation backend using the proposed models.

This article proposes a compact model for the radiation-sensitive field-effect transistor (RADFET). The model represents the basic I–V characteristics of the MOSFET device and includes the effects of threshold voltage shift as a function of absorbed dose and gate bias, gate tunneling current, gate radiation current, dose accumulation, and fading. It accurately represents high-field effects in the gate dielectric of the RADFET device. Both the Fowler–Nordheim gate tunneling current and the radiation-induced gate current are incorporated into the model. The model enables determination of the radiation-induced charge during RADFET operation under high-field injection conditions, thereby improving the precision of accumulated dose readout. The proposed model is fully compatible with SPICE-based circuit simulators and can represent any type of RADFET device, including those with high-k gate dielectrics. Furthermore, the model was developed entirely using open-source circuit simulation tools.

This paper considers physical processes related to the electrostatic discharge (ESD) inducing irreversible failure in the microelectronic devices. The human body model (HBM) destructive voltage evaluation method using the energy equivalence assumption is proposed in this work. This method allows estimating the integrated circuit $\text{HBM}$ rating by the known transmission line pulse (TLP) test result without performing an HBM test. Experimental data confirming the proposed evaluation method is provided.

The purpose of this paper is to investigate a method to derive component metal-metal electrostatic discharge (ESD) rating from its human body model (HBM) ESD rating. Symbolic computations and equivalent circuit simulations are used for this purpose. It can be seen from the components datasheets, that the machine model (MM) rating is often ten times less than the HBM rating. This paper proposes an explanation of this dependence derived fromthermal failure physics. This paper presents a method of the ESD rating estimation based on injected power or charge analysis. This estimation method also could be applied for the CDM and charged board model (CBM) cases. We obtained a good correlation of HBM and MM ratings and a limited correlation of HBM and CBM/CDM ratings. The CBM case for power MOSFET also was considered.

ABSTRACT Current trends in circuit simulation suggest a growing interest in open source software that allows access to more than one simulation engine while simultaneously supporting schematic drawing tools, behavioural Verilog-A and XSPICE component modelling, and output data post-processing. This article introduces a number of new features recently implemented in the ‘Quite universal circuit simulator – SPICE variant’ (Qucs-S), including structure and fundamental schematic capture algorithms, at the same time highlighting their use in behavioural semiconductor device modelling. Particular importance is placed on the interaction between Qucs-S schematics, equation-defined devices, SPICE B behavioural sources and hardware description language (HDL) scripts. The multi-simulator version of Qucs is a freely available tool that offers extended modelling and simulation features compared to those provided by legacy circuit simulators. The performance of a number of Qucs-S modelling extensions are demonstrated with a GaN HEMT compact device model and data obtained from tests using the Qucs-S/Ngspice/Xyce ©/SPICE OPUS multi-engine circuit simulator.

The Qucs Equation-Defined Device was introduce roughly ten years ago as a versatile behavioural simulation component for modelling the non-linear static and dynamic properties of passive components, semiconductor devices and IC macromodels. Today, this component has become an established element for building experimental device simulation models. It's inherent interactive properties make it ideal for device and circuit modelling via Qucs schematics. Moreover, Equation-Defined Devices often promote a clearer understanding of the factors involved in the construction of complex compact semiconductor simulation models. This paper is concerned with recent advances in Qucs-S/Ngspice/XSPICE modelling capabilities that improve model construction and simulation run time performance of Equation-Defined Devices using XSPICE model syntheses. To illustrate the new Qucs-S modelling techniques an XSPICE version of the EPFL EKV v2.6 long channel transistor model together with other illustrative examples are described and their performance simulated with Qucs-S and Ngspice.

Summary Since the introduction of SPICE non‐linear controlled voltage and current sources, they have become a central feature in the interactive development of behavioural device models and circuit macromodels. The current generation of SPICE‐based open source general public license circuit simulators, including Qucs, Ngspice and Xyce©, implements a range of mathematical operators and functions for modelling physical phenomena and system performance. The Qucs equation‐defined device is an extension of the SPICE style non‐linear B type controlled source which adds dynamic charge properties to behavioural sources, allowing for example, voltage and current dependent capacitance to be easily modelled. Following, the standardization of Verilog‐A, it has become a preferred hardware description language where analogue models are written in a netlist format combined with more general computer programming features for sequencing and controlling model operation. In traditional circuit simulation, the generation of a Verilog‐A model from a schematic, with embedded non‐linear behavioural sources, is not automatic but is normally undertaken manually. This paper introduces a new approach to the generation of Verilog‐A compact device models from Qucs circuit schematics using a purpose built analogue module synthesizer. To illustrate the properties and use of the Qucs Verilog‐A module synthesiser, the text includes a number of semiconductor device modelling examples and in some cases compares their simulation performance with conventional behavioural device models. Copyright © 2016 John Wiley & Sons, Ltd.

Circuit simulation is widely used in communication and control equipment hardware design. This article introduces an extended version of the popular Qucs circuit simulator called Qucs-0.0.19S. It is a simulation tool which supports multiple SPICE circuit simulators, including Ngspice and Xyce. The package is equipped with a graphical user interface, component and compact device modelling tools, a choice of simulation engine, and advanced simulation data post-processing facilities. It allows user to construct simulation components using XSPICE "CodeModelling" and to add simulation techniques via Nutmeg scripting. Qucs-0.0.19S is targeted at academic and industrial applications. This paper presents the package software implementation details and a series of typical application studies.

A GNU Octave - based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I-V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I-V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I-V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV © . Selected aspects of the application are presented and discussed.

Qucs (Quite Universal Circuit Simulator) is crossplatform EDA CAD circuit simulation system. Current release is Qucs-0.0.18. Qucs is free and open-source and licensed by GPLv2+. It allows to simulate different circuits from RF to beyond. It has also open XML-based document format. All these factors make Qucs ideal candidate fro academic usage. Qucs usage aspects in electronic engineering education are considered. Active filters are widely used in communication hardware design. New Qucs-0.0.19 release will include a new active filter design tool. The details of implementation of this tool and used filter design algorithms are considered.

A high percentage of analogue integrated circuit designs use voltage domain signal processing techniques. Given the fact that integrated circuit current conveyors are high bandwidth current processing devices, often with superior RF performance when compared to comparable voltage domain devices, it is surprising that the number of current mode integrated circuits available, as standard of-the-shelf industrial items, is so small. This paper introduces equation-defined device and Verilog-A synthesis approaches to the macromodelling of current conveyor integrated circuits. To illustrate the proposed modelling techniques the properties of a number of modular behavioural level current conveyor macromodel cells are described and their performance compared. The material presented is intended for analogue device modellers and circuit designers who wish to simulate current domain integrated circuit designs. It also demonstrates how synthesized Verilog-A functional blocks can be derived from equation-defined device and conventional component subcircuits to form functional, computationally efficient current conveyor macromodels.

In this paper, power MOS transistor behavior under charged board model (CBM) ESD impact is considered. The analysis of the MOSFET failure condition at the CBM ESD event is performed. The CBM equivalent circuit is proposed. The physical parameters of the PCB and device under test are replaced by the lumped RCL circuit. The MOSFET failure voltage calculation method is developed. This method is based on the transient analysis of the CBM ESD equivalent circuit with the general purpose open-source circuit simulator Qucs. This simplified method allows us to calculate CBM ESD voltage dangerous for the MOSFET with less than 20% error for some application cases (pins without ESD protection). CBM ESD tests are performed. Simulation and measurement results are in good match.

Qucs version 0.0.18 was released in August 2014. Since its release the Qucs Development Team has had time to consider the direction the software will take in the near and longer term. Recently, much development work has taken place to remove software bugs, to port the Qucs GUI to toolkit Qt4 from Qt3, to improve the performance and reliability of the qucsator analogue simulation engine, and to improve the Qucs technical and user documentation. This paper presents an overview of the implemented changes and informs the compact modelling community, for the first time, of the possible structure and capabilities of the next release of the Qucs package. Significant new features will include additional compact device modelling capabilities through the inclusion of the Berkeley Model and Algorithm Prototyping Platform (MAPP) linked to Octave and the Qucs/ADMS Verilog-A “turn-key” modelling system, a choice of circuit simulation engine from Qucs built-in software, ngspice and Xyce GPL simulators, plus an increased number of circuit design aids.

This paper is concerned with the development and evaluation of a number of modelling techniques which improve Qucs Harmonic Balance simulation performance of RF compact device models. Although Qucs supports conventional SPICE semiconductor device models, whose static current/voltage and dynamic charge characteristics exhibit second and higher order derivatives may not be continuous, there is no guarantee that these will function without Harmonic Balance simulation convergence problems. The same comment also applies to a number of legacy compact semiconductor device models. The modelling of semiconductor devices centered on non-linear Equation-Defined Devices and blocks of Verilog-A code, combined with linear components, is introduced. These form a class of compact macromodel that has improved Harmonic Balance simulation performance. To illustrate the presented modelling techniques RF diode and bipolar junction transistor macromodels are described and their Harmonic Balance performance simulated with Qucs and Xyce © .