The choice of Verilog-A as an approved semiconductor device hardware description language for IC design has encouraged the interchange of standardised Verilog-A BJT, MOST and BICMOS device models across commercial and FOSS circuit simulators. Recent trends have seen the release of openaccess IC production development kits for digital, analogue, RF and mixed analogue/digital design, completing the "circuit concept to IC production" cycle with FOSS software tools. This paper is concerned with an extension of modelling, simulation and parameter extraction of analogue IC cells using Ques-S/Ngspice and the HIP-G130G2 PDK. To illustrate these techniques an investigation of a CMOS analogue single ended active inductance cell is presented together with simulation output data and extracted model parameters for 1.30nm thin and thick oxide CMOS devices.

The IHP OpenPDK initiative aligns with the EU Chips Act, which provides a fully open and manufacturable SG13G2 BiCMOS technology platform for analog/RF, mixedsignal, and digital IC applications. This initiative aims to bridge the gap between academia, startups, and the semiconductor industry, promoting open collaboration and overcoming economic and technical barriers in semiconductor innovation.

The semiconductor industry continues to grow and innovate; however, companies are facing challenges in growing their workforce with skilled technicians and engineers. To meet the demand for well-trained workers worldwide, innovative ways to attract skilled talent and strengthen the local semiconductor workforce ecosystem are of utmost importance. FOSS CAD/EDA tools combined with free and open-access PDKs can serve as a new platform for bringing together IC design newbies, enthusiasts, and experienced mentors.

This paper presents a new time domain Zener diode compact model for transient noise simulation. SPICE2 and SPIC3 use piece‐wise linear time dependent sources for generating complex waveforms. This approach is not practical when applied to randomly generated noise. Today, through on‐going improvements to freely available circuit simulation tools, SPICE noise generation has moved to a new level. Ngspice, for example, computes white Gaussian noise ‘on‐the‐fly’ as transient simulation progresses. The proposed model has a simple behavioural structure that supports time domain shot, flicker, and thermal noise. The physical properties of the proposed model are introduced in the second section. This is followed by an evaluation of model performance in the third and fourth sections, including static d.c, dynamic charge, and transient noise characterisation. Finally, the fifth section summarises the conclusions of the research.

Schematic capture is an important and popular front-end for circuit simulation. It provides users with a flexible tool that allows circuit diagrams to be drawn and automati-cally converted into textual circuit netlists. Conventional SPICE simulators are essentially engines that input circuit data and simulation command netlists, undertake simulation, and output data for post-processing. This paper is concerned with an advance in circuit schematic capture functionality which allows both SPICE netlists and Verilog-A module code to be simultaneously generated from a device model or circuit schematic. This de-velopment, particularly when combined with SPICE behavioural device modelling, allows automatic generation of Verilog-A device modules rather than going through the manual conversion process from SPICE netlists to Verilog-A code modules. To demonstrate the validity of the reported advances in Qucs-S/Xyce schematic capture a behavioural model and a Verilog-A module for a GaAs MESFET are presented, and their performance described.

The rapid development of new semiconductor materials and devices has highlighted the need for compact modeling and circuit simulation tools that can be easily adapted to accommodate emerging technologies. In most instances device modeling tools employ non-linear behavioural sources and Verilog-A modules for model prototype construction. This paper is concerned with the properties and application of modular user-defined/plugin library toolkit that combines the best features of behavioural source and Verilog-A modeling practice while encouraging user extensions. The toolkit has been implemented as a Qucs/Qucs-S/Xyce modular library that is loadable on demand. To demonstrate its capabilities and flexibility a series of compact device models are introduced and their simulated performance presented and evaluated.

A universal technique for the extraction of device parameters or circuit component values from measured performance data is presented. The proposed method can be used by any circuit simulator that implements parameter sweep features and allows user defined tabulated data with independent voltage, or current, sources. A key feature of the reported extraction process is the use of schematic capture simulation icons, with their sweep parameters tabulated as a list of data points, synthesized from CSV measured data. By overlaying simulation output data on top of measured values, then varying user selected parameter/component values and re-simulating repeatable until the two data sets converge, it becomes possible to extract parameter/component values to within a specified error limit. In this paper FOSS circuit simulators Qucs-S/QucsStudio and the numerical analysis package Octave are used to demonstrate the application of the proposed schematic capture synthesis procedure in the investigate of diode inductance at high forward d.c. bias currents and a.c. signal band width.

The Qucs/QucsStudio and Qucs-S simulators share a common graphical user interface which has slowly evolved into an interactive platform for drawing circuit schematics, controlling simulation and displaying simulation output data and measured device/circuit parameters/properties. This interface acts as a window for accessing circuit simulation software and is in many ways similar to the “White-Boards” that are popular among scientists and engineers for recording ideas when “brainstorming” circuit design or analysis problems. This paper outlines the evolution of the Qucs device modeling and simulation “white-Board” from concept to working media over the fifteen year period that Qucs, QucsStudio and Qucs-S have been under development. The operation of a number of the “White-Board” features are introduced with a compact tunnel diode model and the simulation data obtained from tests using the QucsStudio and Qucs-S software packages.

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.

Equation-Defined Device models (EDD) have become very popular for behavioural modelling of semiconductor and other non-linear devices. Two feature that makes them particularly attractive are their interactive nature and easy testing during the model development process. However, they are less suited for operation as production level models due to their slow simulation performance. This paper presents a new extension to the EDD that offers C++ model performance coupled with the convenience of EDD modelling. The extended form of the EDD is called a Verilog-A EDD or VAEDD for short. It has the same structure as the standard EDD but is built around compiled Verilog-A module code, which in turn is translated to C++ code and dynamically linked to the main body of the simulator code. Essentially a VAEDD is a tiny Verilog-A module with a standardised internal code structure. To demonstrate the interactive approach to compact model building with VAEDD components the design and testing of a high power SiC Schottky barrier diode is included in the main body of the text.

SPICE AC circuit simulation is fundamentally a small signal network analysis of linear or non-linear circuits operating at specified DC bias conditions, where the circuit component values are assumed not to be functions of AC input signal frequency. In the case of RF circuit simulation this assumption can give rise to significant modelling errors. With the recent improvements in General Public License (GPL) circuit simulators this situation is changing, particularly through the introduction of Frequency Dependent Equation-Defined Device (FEDD) models, non-linear current/voltage static and dynamic Equation-Defined Device (EDD) models and user controlled swept signal frequency simulation employing Harmonic Balance steady state analysis. The main purpose of this paper is to introduce a number of novel modelling and circuit simulation techniques that allow, and enhance, the construction of compact device models with embedded behavioural components whose non-linear properties are functions of AC input signal frequency. To demonstrate these new modelling techniques a compact model for a 10 GHz band width spiral inductor integrated on silicon is introduced, its compact model presented, and finally its simulation performance compared with published measured device data.

ABSTRACT Current trends in circuit simulation suggest a growing interest in open source software that allows access to more than one simulation engine while simultaneously supporting schematic drawing tools, behavioural Verilog-A and XSPICE component modelling, and output data post-processing. This article introduces a number of new features recently implemented in the ‘Quite universal circuit simulator – SPICE variant’ (Qucs-S), including structure and fundamental schematic capture algorithms, at the same time highlighting their use in behavioural semiconductor device modelling. Particular importance is placed on the interaction between Qucs-S schematics, equation-defined devices, SPICE B behavioural sources and hardware description language (HDL) scripts. The multi-simulator version of Qucs is a freely available tool that offers extended modelling and simulation features compared to those provided by legacy circuit simulators. The performance of a number of Qucs-S modelling extensions are demonstrated with a GaN HEMT compact device model and data obtained from tests using the Qucs-S/Ngspice/Xyce ©/SPICE OPUS multi-engine circuit simulator.

Qucs-S is a spin-off of the Qucs cross-platform circuit simulator. S letter indicates SPICE. The purpose of the Qucs-S subproject is to use free SPICE circuit simulation kernels with the Qucs GUI. It merges the power of SPICE and the simplicity of the Qucs GUI. Qucs intentionally uses its own SPICE incompatible simulation kernel Qucsator. It has advanced RF and AC domain simulation features, but most of the existing industrial SPICE models are incompatible with it. Qucs-S is not a simulator by itself, but it requires to use a simulation backend with it. The schematic document format of Qucs and Qucs-S are fully compatible. Qucs-S allows to use the following simulation kernels with it: Ngspice is recommended to use. Ngspice is powerful mixed-level/mixed-signal circuit simulator. The most of industrial SPICE models are compatible with Ngspice. It has an excellent performance for time-domain simulation of switching circuits and powerful postprocessor. XYCE is a new SPICE-compatible circuit simulator written by Sandia from the scratch. It supports basic SPICE simulation types and has an advanced RF simulation features such as Harmonic balance simulation. SpiceOpus is developed by the Faculty of Electrical Engineering of the Ljubljana University. It based on the SPICE-3f5 code Qucsator as backward compatible.

The Qucs Equation-Defined Device was introduce roughly ten years ago as a versatile behavioural simulation component for modelling the non-linear static and dynamic properties of passive components, semiconductor devices and IC macromodels. Today, this component has become an established element for building experimental device simulation models. It's inherent interactive properties make it ideal for device and circuit modelling via Qucs schematics. Moreover, Equation-Defined Devices often promote a clearer understanding of the factors involved in the construction of complex compact semiconductor simulation models. This paper is concerned with recent advances in Qucs-S/Ngspice/XSPICE modelling capabilities that improve model construction and simulation run time performance of Equation-Defined Devices using XSPICE model syntheses. To illustrate the new Qucs-S modelling techniques an XSPICE version of the EPFL EKV v2.6 long channel transistor model together with other illustrative examples are described and their performance simulated with Qucs-S and Ngspice.

Qucs-S is a spin-off of the Qucs cross-platform circuit simulator. S letter indicates SPICE. The purpose of the Qucs-S subproject is to use free SPICE circuit simulation kernels with the Qucs GUI. It merges the power of SPICE and the simplicity of the Qucs GUI. Qucs intentionally uses its own SPICE incompatible simulation kernel Qucsator. It has advanced RF and AC domain simulation features, but most of the existing industrial SPICE models are incompatible with it. Qucs-S is not a simulator by itself, but it requires to use a simulation backend with it. The schematic document format of Qucs and Qucs-S are fully compatible. Qucs-S allows to use the following simulation kernels with it: Ngspice is recommended to use. Ngspice is powerful mixed-level/mixed-signal circuit simulator. The most of industrial SPICE models are compatible with Ngspice. It has an excellent performance for time-domain simulation of switching circuits and powerful postprocessor. XYCE is a new SPICE-compatible circuit simulator written by Sandia from the scratch. It supports basic SPICE simulation types and has an advanced RF simulation features such as Harmonic balance simulation. SpiceOpus is developed by the Faculty of Electrical Engineering of the Ljubljana University. It based on the SPICE-3f5 code Qucsator as backward compatible.

is a new variant of the popular Qucs GPL circuit simulation package. It has been under development for the last two years. In September 2016 the development team proposes to release for general use, Release Candidate 7 (RC7). RC7 is the culmination of the last few months development, bringing to the circuit simulation and modelling scene, the most stable version of the package released so far. RC7 also includes an extensive Qucs-S Help document which should assist in the use of the package for circuit simulation and compact device modelling. The purpose of this presentation is to outline the simulation and modelling facilities offered by Qucs-S, to demonstrate features not normally associated with SPICE, and to show how can be applied to modelling emerging technology devices. The latter will be introduced using GaN devices as examples of current compact modelling practice.

Qucs-0.0.19-S-RC6 Simulation and Compact Device Modelling Tools Introduction to the Qucs GPL Verilog-A Module Synthesizer Qucs modelling of the ”Efficient Power Corporation (EPC)” GaN EPC2001 Power Transistor Qucs Verilog-A Modeling of the ”MIT Virtual Source GaN-RF HEMT Compact Device Model 1.0.0”: Problems Simulating with ADMS; Workarounds and Typical Simulation Data Qucs-0.0.19-S-RC6 XSPICE Code Modeling package Qucs-0.0.19-S-RC6/Ngspice/Xyce Circuit Analysis and Compact Device Parameter Extraction from Manufacturers Data or Measurements Controlled by Octave Script Files Summary

Summary Since the introduction of SPICE non‐linear controlled voltage and current sources, they have become a central feature in the interactive development of behavioural device models and circuit macromodels. The current generation of SPICE‐based open source general public license circuit simulators, including Qucs, Ngspice and Xyce©, implements a range of mathematical operators and functions for modelling physical phenomena and system performance. The Qucs equation‐defined device is an extension of the SPICE style non‐linear B type controlled source which adds dynamic charge properties to behavioural sources, allowing for example, voltage and current dependent capacitance to be easily modelled. Following, the standardization of Verilog‐A, it has become a preferred hardware description language where analogue models are written in a netlist format combined with more general computer programming features for sequencing and controlling model operation. In traditional circuit simulation, the generation of a Verilog‐A model from a schematic, with embedded non‐linear behavioural sources, is not automatic but is normally undertaken manually. This paper introduces a new approach to the generation of Verilog‐A compact device models from Qucs circuit schematics using a purpose built analogue module synthesizer. To illustrate the properties and use of the Qucs Verilog‐A module synthesiser, the text includes a number of semiconductor device modelling examples and in some cases compares their simulation performance with conventional behavioural device models. Copyright © 2016 John Wiley & Sons, Ltd.