We present a simple and reliable hybrid packaging of rigid electrochemical transducers and flexible foil having electrical connections. Among a large number of biochemical transducers, we target in this work two types of transducers: 3-electrode systems and ion selective field effect transistors (ISFET). The hybrid packaging ensures several requirements such as: biocompatibility to biological analytes, precise tight encapsulation, protection of transducers surface, mechanical stability, reliable electrical contact and light shielding of sensitive parts. The proposed hybrid packaging of biochemical transducers is based on a flip-chip bonding process, which necessitates low-cost materials, a reduced number of processing steps as well as compatibility to common roll-to-roll (R2R) processes.

Here, we report flip-chip bonding processes based on Anisotropic Conductive Film (ACF) and Sn-Ag-Cu (SAC) solder implemented for bonding three test chips (two Silicon, Si ICs on either side of an Indium Phosphide, InP IC) in series on $25{\mu}\mathrm{m}$ thick polyimide foil substrates. Si ICs were bonded only with SAC solder, whereas both SAC and ACF were applied for the flip-chip integration of the fragile InP chips. RF measurements were then performed on the impedance controlled paths across the polyimide foil of the fabricated assemblies to evaluate as well as to compare the RF performance of ACF and SAC solder in terms of the differential S 21 parameter. The measurements revealed that when ACF is employed for interconnecting the InP chip and SAC solder for the two Si chips, a higher 3 dB bandwidth of 42 GHz was obtained whereas a 3 dB bandwidth of only 31 – 34 GHz was measured when only SAC solder was used for bonding all three ICs. These measurement results confirm that a higher bandwidth can be obtained from the assemblies when ACF is used as the interconnection material. Therefore, it can be concluded that the ACF based integration technology could be favored over solder processes for bonding high performance multi Gbit/s subassemblies, especially with higher density of contact pads.

The growing interest towards thinner and conformable electronic systems has attracted significant attention towards flexible hybrid electronics (FHE). Thin chip-foil packages fabricated by integrating ultra-thin monocrystalline silicon integrated circuits (ICs) on/in flexible foils have the potential to deliver high performance electrical functionalities at very low power requirements while being mechanically flexible. However, only very limited information is available regarding the fatigue or dynamic bending reliability of such chip-foil packages. This paper reports a series of experiments where the influence of the type of metal constituting the interconnects on the foil substrates on their dynamic bending reliability has been analyzed. The test results show that chip-foil packages with interconnects fabricated from a highly flexible metal like gold endure the repeated bending tests better than chip-foil packages with stiffer interconnects fabricated from copper or aluminum. We conclude that further analysis work in this field will lead to new technical concepts and designs for reliable foil based electronics.

The emerging Internet-of-Everything (IoE) framework aims to revolutionise human-machine interaction where billions of sensors and actuators placed on almost every physical object will be tasked to communicate with each other. A substantial fraction of these devices will be placed on locations that would undergo repeated bending deformation (such as sensors for prosthetics, human body and robots) or on curved surfaces (like interior as well as exterior of automobiles, buildings and industrial equipment). Therefore, flexible sensors and actuators delivering high performance at low power requirements and manufactured at low cost will be the key for successful implementation of IoE. Though massive developments achieved in printed and organic electronics have enabled them to fulfil the required flexibility and low cost demands of IoE applications, printed and organic electronics often fall short of the high performance and low power requirements demonstrated by silicon ICs. Flexible chip foil packages fabricated by integrating ultra-thin bare silicon ICs fulfil the aforementioned demands posed by IoE applications and therefore, they are often considered as potential enablers of IoE. Here, we present an innovative roll-to-roll manufacturing compatible low cost approach for direct metal interconnection and integration of ultra-thin silicon ICs. The thickness of the fabricated flexible packages with the integrated and interconnected ultra-thin ICs were as thin as 100 μm. Electrical measurements conducted on the 60 fabricated samples with interconnected flexible ultra-thin ICs revealed a very promising yield of 94%.

An innovative, advanced packaging concept for integrating thin dies is presented. The novel packaging technique is based on a flip chip approach where an anisotropic conductive adhesive was used to bond thin dies on a flexible, polymeric interposing substrate. After bonding of the chip, a flexible potting material was coated over the chip and the substrate to complete the housing of the package. The package thus realised was mechanically bendable and it had a thickness of ~140 micrometer. Since the package is free of any wire bonds, overall heights of less than 200 micrometer can be realized. The paper describes the process flow followed for preparing the flexible interposer demonstrator samples. Furthermore, assembly techniques for integrating the flexible interposers on a flexible wiring substrate are discussed. Besides, mechanical and environmental reliability tests were performed with the samples which revealed a good reliability of the samples.

With the emergence of the Internet-of-Things (IoT) and wearable devices in the recent years, Flexible Hybrid Electronics (FHEs) has attracted significant attention. Chip-foil packages (also known as flexible interposers) fabricated by integrating ultra-thin silicon ICs onto or embedded into polymer foils comprising of metal interconnects (wiring lines, through hole via interconnects etc.) for powering up the system and transmission of data signals / IO commands are ideal candidates for FHE integration. The principal advantages of chip-foil packages over standard Surface Mount Device (SMD) components are their bendability and conformability. However, the behavior of chip-foil packages under repeated bending must be analyzed in detail through extensive investigations to enable the transfer of the technology from research labs to industrial manufacturing platforms. Hence, we conducted two different types of bending tests to examine the repeated or dynamic bending reliability of the wiring lines and the via interconnects of the chip-foil packages. The experimental results highlight the need for design optimized dimensioning of the wiring lines and the via interconnects for manufacturing FHEs with high performance and good dynamic bending reliability. Such results complement the state-of-the-art information available regarding the electrical as well as mechanical reliability of chip-foil packages and are required as essential information for establishing guidelines for handling chip-foil packages during integration as well as for producing FHEs that are more reliable.

We report our results on the comparative studies of the influence of chip thickness and dicing technique on the mechanical reliability of flip-chip bonded ultra-thin chip-on-foil (COF) assemblies under two different types of recurrent bending, free form bending and fixed radius bending (bending radius-5 mm). Free form bending experiments conducted on 28 μm and 250 μm COF assemblies demonstrated the improvement in fatigue reliability of the foil wiring lines of the COF assemblies with the reduction in chip thickness. Experimental results of the fixed radius bending tests revealed that COF assemblies with 12 μm chips endured the bending tests almost 2 times better than COF assemblies with 20 μm chips. Furthermore, COF assemblies with plasma diced chips showed better dynamic bending reliability than wafer sawn chips during fixed radius bending tests. Optical Microscopy and Computed Tomography analyses indicated that the dominant cause of failure occurring in COF assemblies was the rupture of wiring lines rather than the interconnect delamination or chip cracking. Besides, Atomic Force Microscopy analysis of the sidewalls of 20 μm ultra-thin chips revealed that the sidewalls of plasma diced chips were 3 times smoother than the wafer sawn chips.

We present technological results on the embedding of ultra-thin microcontroller ICs in flexible film substrates. The novel concept is based on the following technologies: face-up chip mounting in cavities on film laminates, photo-lithographic patterning of vias and interconnects embedding in polymer layer and compatibility with both sheet and roll-to-roll processing. The paper briefly reviews the benefit of embedding for ultra-thin dies in terms of mechanical robustness. For the technological demonstration, we used 25μm thin microcontroller IC and 50μm polyimide film substrates. Electrical interconnections were realized by sputtering of metal layers. Photolithography was performed on “wafer level” using aligner photomasks and a photo-sensitive polymer of 10μm thickness for embedding. The embedding process resulted in a mechanically flexible fan-out chip package of a thickness below 100μm. Perspectives and technological requirements for roll-to-roll manufacture as well as cost estimation for this kind of Thin Chip Foil Package are explained and discussed. Furthermore, we report our recent work on the development of an in-situ bending and electrical test equipment for flexible film modules. The new set-up was evaluated using ultra-thin test chips with daisy chain patterns that were ACA flip-chip bonded onto Polyimide films. It was found that reducing the chip thickness from 28μm to 12μm lead to a strong increase in mechanical strength of the chip-on-film (COF) assemblies tested under recurrent bending.

We present our results on the analysis of electrical performance of Flip-Chip bonded thin Silicon chip-on-foil assemblies during bending. A custom made bending machine was utilized to bend the test samples and the electrical resistance of the Daisy Chain structures were measured during the tests. Resistance measurements confirmed the failure of the test samples after about 2000 bending cycles.

In this paper we present a technology developed for reliable electrical interconnection on film substrates and between vertically stacked film layers. Applying through-hole via technologies for 3D foil stacks enables multi-functionality and RF performance combined with open form-factor and very cost-efficient manufacturing of conformable electronic modules. The manufacture of fine line metal patterns (line /space geometries below 20μm) on film substrates is performed by cost-effective roll-to-roll technology. Furthermore procedures and technologies for handling and lamination of film based sub-modules have been developed. Also the manufacture and handling of ultra-thin and flexible integrated circuits has been combined with placement of SMD type passive and with integrated printed passive components in the same technology.

The described application directs the integration of capacitive and resistive sensors for environmental parameters monitoring (CO2, relative humidity, dew point and temperature) in low cost applications which can be made on flexible substrate, which was developed in the European FP7 project INTERFLEX [1]. This type of applications on plastic substrates requires a reduction of amount and type of components in order to reduce costs through simplification of assembly processes as well as enhancement of the reliability.This paper describes a very simple low power and cost effective architecture for readout of capacitive and resistive sensors, which uses few external components, exploiting a STMicroelectronics STM8L15x microcontroller and sensors developed by Fraunhofer Research Institution for Modular Solid State Technologies (EMFT). (C) 2014 Published by Elsevier Ltd.

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The paper reports on a self-assembly process that enables both self-alignment of microelectronic devices and self-interconnection of devices with the surrounding electrical wiring. The complete process was successfully demonstrated using state-of-the-art RFID devices (radio frequency identification device) which were self-connected to four metal pads on polymer foil substrates. The new self-assembly concept comprises the following steps: mask-less plasma patterning process to define target areas for die assembly on polymer tapes, application and self-alignment of a liquid assembly medium at the target area, dropping of the chip device onto the assembly liquid, self-orientation of the chip with respect to the contact pads and finally heat induced bonding and interconnection of the device.

AbstractWasser ist Leben und so ist es in Deutschland auch das am besten kontrollierte Lebensmittel. Verunreinigungen aller Art sind darin tabu. Besonders Bakterien sind als lebende Organismen im „Lebensmitteln Nr. 1”︁ nicht willkommen. Wasserversorger müssen mit regelmäßigen Tests nachweisen, dass ihr Wasser frei von den Kleinstlebewesen ist. Die Tests dazu dauern bisher noch mehrere Tage und dürfen nur von geschultem Personal im Labor durchgeführt werden — für die Versorger und die Verbraucher ein unbefriedigendes Verfahren, denn es ist teuer und zeitaufwendig. Eine effizientere Messmethode entwickeln Forscher derzeit in einem Förderprojekt des BMBF.

A self-assembly process for the two-dimensional arrangement of micrometer sized silica beads on glass slides was developed. It is based on the hybridization of two single stranded DNA-oligonucleotides to a DNA double helix. To prepare for the self-assembly process the silica beads as well as the glass slides were modified covalently with matching DNA-molecules. The patterned areas on the slides were defined by printing DNA-molecules with an optimized micro contact printing procedure using agarose gel stamps. In the following hybridization experiment the addressed beads self-assemble selectively on the matching areas of the glass substrate. Control experiments with mismatching DNA-oligonucleotides showed that silica beads tend to adhere strongly to the glass surfaces. Washing conditions must be controlled carefully to differentiate between hybridized beads and non-specifically bound beads. With regard to the use of this method in microelectronic chip assembly it could be shown that the salt concentration during the hybridization step can be reduced drastically without affecting the hybridization reaction.

The automated 10-channel capillary chip immunodetector (10K-IDWG) is a prototype, which has been developed for automatically operated biological agents (BA) point detection. The current technology uses a chemiluminescence capillary immunoassay (EIA) technique in combination with integrated microfluidics and allows the highly sensitive and rapid detection and preliminary identification of multiple BA in aqueous solutions in the laboratory. The chemiluminescence capillary EIA are performed within a disposable capillary chip containing 10 fused-silica capillaries arranged in parallel coated with selected capture antibodies. A multianode-photomultiplier array is used to detect chemiluminescence intensity in each capillary. Reservoirs for reagents and buffers and a waste disposal reservoir are integrated. This paper describes the technology of the 10K-IDWG and its evaluation with three different BA, the toxin staphylococcal enterotoxin B (SEB), the bacterial analyte Escherichia coli (E. coli) O157:H7 as a model for bacterial pathogens, and the bacteriophage M13 as a model for virus pathogens. The 10K-IDWG is able to detect the above mentioned three BA in an aqueous sample within 29 min (single analyte-detection and multiplexing). Limits of detection (LOD) are 0.1 ng/ml for SEB, 10(4)cfu/ml for E. coli O157:H7, and 5x10(5) pfu/ml for M13. Cross reactivities between the three assays were not observed.