During the last few decades, the semiconductor industry has been able to scale device performance up while driving costs down. What started off as simple geometrical scaling, driven mostly by advances in lithography, has recently been accompanied by advances in processing techniques and in device architectures. The trend to combine efforts using process technology and lithography is expected to intensify, as further scaling becomes ever more difficult. One promising component of future nodes are "scaling boosters", i.e. processing techniques that enable further scaling.An indispensable component in developing these ever more complex processing techniques is semiconductor process modeling software. Visualization of complex 3D structures in SEMulator3D, along with budget analysis on film thicknesses, CD and etch budgets, allow process integrators to compare flows before any physical wafers are run. Hundreds of "virtual" wafers allow comparison of different processing approaches, along with EUV or DUV patterning options for defined layers and different overlay schemes. This "virtual fabrication" technology produces massively parallel process variation studies that would be highly time-consuming or expensive in experiment.Here, we focus on one particular scaling booster, the fully self-aligned via (FSAV). We compare metal-via-metal (me-via-me) chains with self-aligned and fully-self-aligned via's using a calibrated model for imec's N7 BEoL flow. To model overall variability, 3D Monte Carlo modeling of as many variability sources as possible is critical. We use Coventor SEMulator3D to extract minimum me-me distances and contact areas and show how fully self-aligned vias allow a better me-via distance control and tighter via-me contact area variability compared with the standard self-aligned via (SAV) approach.

In this paper we present the concept of the Fully Self Aligned Via (FSAV) with motivation of achieving manufacturable litho process windows for patterning vias in 5nm-node interconnects. A process flow is proposed for FSAV which includes metal recess etching and insertion of an etch stop layer. Integration challenges for this flow are addressed and solutions demonstrated with complementary capacitance simulation.

Directed Self Assembly (DSA) has gained increased momentum in recent years as a cost-effective means for extending lithography to sub-30nm pitch, primarily presenting itself as an alternative to mainstream 193i pitch division approaches such as SADP and SAQP. Towards these goals, IMEC has excelled at understanding and implementing directed self-assembly based on PS-b-PMMA block co-polymers (BCPs) using LiNe flow [1]. These efforts increase the understanding of how block copolymers might be implemented as part of HVM compatible DSA integration schemes. In recent contributions, we have proposed and successfully demonstrated two state-of-the-art CMOS process flows which employed DSA based on the PS-b-PMMA, LiNe flow at IMEC (pitch = 28 nm) to form FinFET arrays via both a 'cut-last' and 'cut-first' approach [2-4]. Therein, we described the relevant film stacks (hard mask and STI stacks) to achieve robust patterning and pattern transfer into IMEC's FEOL device film stacks. We also described some of the pattern placement and overlay challenges associated with these two strategies. In this contribution, we will present materials and processes for FinFET patterning and integration towards sub-20 nm pitch technology nodes. This presents a noteworthy challenge for DSA using BCPs as the ultimate resolution for PS-b-PMMA may not achieve such dimensions. The emphasis will continue to be towards patterning approaches, wafer alignment strategies, the effects of DSA processing on wafer alignment and overlay.

Over recent decades, continuous reductions in the scale of fieldeffect transistors in accordance with Moore’s law, which states that the number of transistors in an integrated circuit doubles every two years, have enabled continuous increases in device performance and transistor density.1–3 Currently, state-of-theart devices are based on structural elements with dimensions of 7nm or even 5nm (N7/N5). The highest-resolution patterns required for N7/N5 devices are silicon fins with a pitch of 18–28nm and metal layers with a pitch of 24–32nm. These dimensions far exceed the resolution attainable with 193 immersion (193i) lithography. Extreme UV lithography might be an alternative process for the formation of lines and spaces, but is expensive and not entirely ready for use in production.4 To overcome the limitations of lithography, multiple patterning methods—litho-etch or self-aligned multiple patterning— were used in the last four stages of device miniaturization based on nodes of 10–28nm (N10–N28).5, 6 To achieve the specifications for fins in N7/N5 devices, we need a self-aligned quadruple patterning (SAQP) method that provides a critical dimension (CD) of about 7nm, a CD uniformity (CDU) and pitch walk of 0.5nm (3 sigma), and a line width roughness (LWR) and line edge roughness (LER) of 1.4 and 1.2nm, respectively. We have developed a low-cost SAQP method that has the potential to meet these requirements for fins. We started with a 193i lithography pattern with a pitch of 90nm and lines and spaces of 40 and 50nm, respectively, which we transferred onto a mandrel. Then we deposited silicon dioxide (SiO2) spacers by Figure 1. Simulation images of the stages of self-aligned quadruple patterning (SAQP) obtained using Coventor SEMulator3D software show, from left to right: patterning of the first core (brown) onto a mandrel (green); deposition of silicon dioxide (SiO2) (light blue) by atomic layer deposition (ALD); etching of the first spacers; etching of the mandrel to produce the second core; further deposition of SiO2 by ALD; and etching of the second spacers and silicon nitride pad (dark blue). The scale bars represent 30nm.