Ruthenium is viewed as a promising alternative to Cu and Co interconnect metals at M0/M1 interconnect layers due to its lower effective resistivity in highly-confined layers and vias, as well as its resistance to diffusion into porous low-k dielectrics and to electromigration. Atomic layer deposition of Ru has been reported with a variety of precursors, but the search for a Ru ALD process with a close-to-bulk (~7 μΩ·cm) resistivity is ongoing, with special interest in a process that can selectively-deposit low-resistance Ru films without passivants. In this work, Ru films with close-to-bulk resistivity deposited using Ru(CpEt)2 were investigated using four-point-probe resistivity measurements, Xray photoelectron spectroscopy (XPS) for chemical analysis, X-ray diffraction/reflectometry (XRD/XRR) for grain size and thicknesses, and scanning electron microscopy (SEM) and atomic force microscopy (AFM) for film morphology.
SAM (Self-Assemble-Monolayer) is a material with selectively growth on only metal or dielectric film. Moreover, SAM can have functionality such as growth inhibitory property of ALD film and Cu barrier property. The barrier/liner metal at Via bottom can be removed by SAM which has an ALD film growth inhibitory property, and by using the ELD-Cu(Electro-Less-Deposition) Pre-Via-Fill process, Cu volume at Via can be increased and Via resistance can be reduced. In this study, we have introduced the process that can reduce the process steps and reduce Via resistance by using SAM with Cu barrier properties.
We present a methodology for predicting line-to-line reliability of Air-Gap schemes, which accounts for line-edge roughness and electric field enhancement. Our model is calibrated to the intrinsic reliability properties of the Air-Gap interface dielectrics, which are characterized by performing time-dependent dielectric breakdown measurements on planar capacitors. We validate our model to experimental TDDB data from Ru/Air-Gap semi-damascene interconnects and predict that deeper Air-Gaps, extending into the bottom interlayer dielectric, can significantly boost the reliability of Air-Gaps schemes.
Ru semi-damascene has been recently considered as a promising candidate to replace the conventional Cu dual damascene to meet the continued RC scaling needs in sub-2nm technology nodes. In this work, Ru lines with critical dimension of 9–10 nm and AR 3–6 targeting MP18-MP26 were fabricated in IMEC 300-mm pilot line using EUV-SADP technique and subsequent direct etch of Ru films for the first time. We demonstrate the optimizations made in patterning, metal etch, and clean that enabled the successful fabrication of Ru lines. Single line resistance of 10μm Ru with AR 3 shows that >90% of the devices meet the resistance target of <700 Ω/μm for MP20–26 and ~50% for MP18. Leakage current measurements between the core-defined and gap-defined Ru lines show >90% of devices meet the leakage target of 10 −11 A/μm.
Chemical mechanical polishing (CMP) process have been heavily utilized in throughout the semiconductor manufacturing processes from front-end to back-end for decades. However, CMP process is still in its early stage for advanced packaging because of the difficulties observed with implementation of CMP process such as: low removal rate, poor selectivity, and elevated surface roughness and defects on the organic polymer film. Nevertheless, CMP process is becoming an essential part of the 2D advanced packaging and beyond in order to achieve smaller pitch and improve re-distribution layer (RDL) process.In this paper, we focus on highly tunable removal rate and selectivity, and low defectivity performance slurry for epoxy mold compound (EMC) with silica filler and Cu pads.
Titanium nitride (TiN) thin films are utilized as diffusion barriers for Co and W metal layers as well as the gate metal barrier in CMOS and memory devices due to the material’s low resistivity; TiN is also used as a coating for hard disk drives [1] . Low resistivity TiN in commercial devices has been deposited by plasma-enhanced ALD (PE-ALD) and by physical vapor deposition. However, for high aspect ratio features and horizontal vias, deposition by thermal ALD is needed to enhance the conformality of the deposition process. In the present work, it is shown that the resistivity can be decreased below 220 uΩ-cm with a non-halogenated precursor at 425 °C by using a Ti precursor with high thermal stability and by reducing the oxygen and carbon contents in the films using a highly reactive co-reactant, anhydrous hydrazine (N 2 H 4 ).
To overcome the micro loading effect that happens during M2 trench etch, an Al2O3 etch stop layer is successfully implemented in our test vehicle with minimum 21nm metal pitch dual-damascene interconnects. Two integration challenges are investigated: via opening difficulty with 2nm Al2O3 layer and undercut issue with 5nm Al2O3 layer. Potential solutions are proposed accordingly. Post Ru metallization, good morphological and electrical results are demonstrated for the split with 5nm Al2O3.
This paper reports the effect of composition deviation of CuAl 2 on electromigration (EM) property. EM property was measured in the temperature range of 225–325 °C at a current density of 1 MA/cm 2 . At 275 °C, the void formation rate of Al-rich sample was found to be 1.1–1.2 times faster than that of stoichiometric samples, while it was reduced to 1/5 for Cu-rich samples. The activation energy of Al-rich and stoichiometric samples is found to be 1.16 eV, while that of Cu-rich sample is 1.59 eV. These results show that shifting the composition to Cu-rich side enhances the electromigration properties and the composition has been found to have a significant effect on electromigration of intermetallic compounds.
In this work, the microstructural and stress evolution of Mo and Ru films is studied at relevant temperatures for interconnect processing. Wafer bow measurements, transmission electron microscopy (TEM), in-situ XRD (IS-XRD), and microelectromechanical systems (MEMS) were used to determine stress and thermal stress evolution for 10 to 30 nm thick films. We show that Mo and Ru present a complex evolution of the stress evolution during thermal cycling that can be linked to the creation and diffusion of point defects.
Cu to Cu direct bonding at low temperature has required the driving force of the Cu films to self-diffuse each other. In this study, high defect density Cu was optimized with a mechanical property of the self-annealing phenomena. Furthermore, the mechanism of the defect generation was studied with electrochemical analysis. Based on the analytical study, Cu to Cu bonding with the high defect density Cu, which had high tensile strength, was successfully conducted at 250°C bonding temperature.
Two-dimensional (2D) materials have been suggested to offer a viable route towards further miniaturization of interconnect technology as new diffusion barriers (DBs), replacing current industry standards at low thickness regime. We investigate new copper DBs to be used in back end of line (BEOL) interconnect structures, based on 2D materials grown on a large scale. The films are characterized using transmission electron microscopy, X-ray photoelectron spectroscopy and Raman spectroscopy to verify their structural quality and chemical composition. An experimental protocol is presented to assess the performance of these films as DBs, including a device fabrication scheme and a measurement scheme that both allow for the comparison of different barriers. This study establishes the difference in barrier properties as a function of film thickness based on their different crystal structure, comparing 2D materials with industry standard TaN barriers, thus evaluating the potential of 2D materials for future, scaled down, interconnect technology. This screening protocol also enables optimization of the growth conditions for improved DBs.
High aspect-ratio (AR) 3-level Supervias (SV), with a minimum bottom CD of 15.5 nm and AR = 7.7 are successfully integrated in a 3nm node chip. 3-level SV directly connects M x with M x+3 metal layers, without connecting to the intermediate two metal layers. Enabling such high AR SV is achieved by fine tuning the SV etch process to guarantee uniform SV landing and a straight vertical profile. Electrical results show that 3-level Kelvin SVs provide an average resistance of 58 Ω, yielding > 95 % for the best conditions, improving our previously reported yield values of 2-level with enhanced AR [1]. 3-level SVs gave a resistance 13% lower than the conventional 2-level stacked via configuration [2]. Metallization stack used was 0.3 nm of ALD TiOx as an adhesion layer, followed by a Ru CVD deposition of 70 nm. Thermal shock tests of 500 hours, between −50 °C and 125 °C, performed on intervals of 15 min each, showed that the Kelvin resistance values remained virtually unchanged. Therefore, 3-level SV are stable after thermal shock tests, proving that they are a robust scaling booster for the 3nm node.
Low resistivity metal wiring and interconnects are increasingly challenged by size-dependent effects with downscaling for the next generation back end of line (BEOL) requirements. Ruthenium is considered a strong candidate although it has challenges. However, tungsten wiring is well established, widely used in DRAM, and is relatively easier to integrate. We demonstrate the novel use of ion beam deposition (IBD) to control the microstructural features, such as phase, texture, and grain size distribution of W and Ru thin films. Using IBD to drive highly selective microstructures, we have demonstrated low resistivities of <11 μΩ-cm for <20nm thick as-deposited (0001) oriented Ru and <9 μΩ-cm for <20nm thick as-deposited (110) oriented α-W. IBD deposition of W yielding epitaxial-like textured α-110 thin films was identified as showing favorable resistivity scaling. We propose the IBD of highly oriented (110) α-W as a lower cost, easily integrable solution for next generation wiring.
In this work we have fabricated 28nm-pitch dual damascene structures using EUV single exposure for both via and metal. Ruthenium metallization has been used for the via-trench fill and final structures are characterized with Voltage Contrast metrology. By properly designing test structures with programmed shifts between via and metal and tip-to-tip variations it is possible to determine the design rules needed to obtain high yield in this process before electrical measurements.
This paper introduces ALD Mo as a potential replacement for W and Co as the conductor for logic MOL interconnects. 10nm ALD Mo without a liner and barrier has a very good adhesion on SiO 2 , SiN and SiCO dielectrics with resistivity as low as 19–22 μm.cm. We demonstrate for the 1 st time a liner/barrier less ALD Mo fill capability in high aspect ratio trenches down to 10nm CD and show that ALD Mo does not drift into SiO 2 and SiCO.
In this work, the impact of metal hybrid height (H^2) and airgap (AG) scaling boosters are evaluated based on an enhanced Ring Oscillator (RO) framework that accounts for Place and Route (PnR) aspects of the back end of line (BEOL) interconnects. When targeting best performance, extended AG with high aspect ratio (AR) lines appears to be the optimal choice as it allows reducing both capacitance (C) and resistance (R). Combining AG with H^2 provides minimum C at an increased R making it more suitable for power optimization.
Cryo-CMOS circuit performance at 4K including both BEOL and FEOL characteristics has been investigated in a 65nm bulk CMOS for the first time. ON-current (Ion) of n/pMOSFET are improved +25%/+9% with excellent gate modulation (Ion/Ioff=~109). Cu line/via resistances decrease with temperature due to reduction of phonon scattering, and −75%/−20% lower resistances are obtained at 4K. It is revealed that there is no inter-line capacitance change and no severe Joule heating effect (JHE) of Cu BEOL at 4K. The newly developed 4K-SPICE model including BEOL characteristics enables accurate CMOS circuit design at 4K, giving 5 ~ 40% faster operation of RC line with clear dependence on driver-size and interconnect-load.
Regarding the resistance reduction in the fine metal line of the semiconductor device, the annealing effect by the excimer laser was confirmed. Excimer laser was irradiated to Cu and Ru as fine metal line materials, and the change in resistivity and the surface condition (change in the metal grain size) were confirmed. As a result, in Cu, the grain size doubled, and the resistivity decreased by about 20%. In Ru, the grain size expanded by about 1.2 times, and the resistivity decreased by about 10%. This experimental evaluation was performed by a KrF excimer laser with a pulse width of 82 ns and was found to have the lowest resistance just before the irradiation damage threshold (melting or ablation initiation value) in both cases.
In this work we evaluate low via resistance options in 21 – 24nm pitch structures by comparing Ru, W versus Cu. A bottom barrierless Cu DD metallization is created using a selective TaN deposition. In MP24, this selective barrier Cu metallization system shows up to a 20% via resistance reduction as compared to conventional Cu DD fill with 1.5nm TaN barrier. The via resistance evaluation of the selective barrier Cu in MP21 shows that the system can be an option for further extension of Cu interconnects while keeping the resistance under control. The line and chain resistance comparison towards barrierless DD Ru shows that the SB Cu metallization is competitive in terms of performance and therefore the preferred way forward for MP24 DD structures.
This paper presents a minimum pitch single patterning process for 5nm node back-end-of-line (BEOL) integration based on extreme ultraviolet (EUV) lithography with quasar illumination and optical proximity correction (OPC). OPC was applied for improving stochastic printing failures such as single-line-open (SLO) and micro-bridges. The optimized OPC effectively improved 94% of SLO and 96% of micro-bridges. The reliability requirement of the time-dependent dielectric breakdown (TDDB) was also satisfied for 5nm node BEOL integration, and this new process would be implemented for sub-5nm node device manufacturing.
