We present the fabrication of 4 K-scale electrochemical random-access memory (ECRAM) cross-point arrays for analog neural network training accelerator and an electrical characteristic of an 8 × 8 ECRAM array with a 100% yield, showing excellent switching characteristics, low cycle-to-cycle, and device-to-device variations. Leveraging the advances of the ECRAM array, we showcase its efficacy in neural network training using the Tiki-Taka version 2 algorithm (TTv2) tailored for non-ideal analog memory devices. Through an experimental study using ECRAM devices, we investigate the influence of retention characteristics on the training performance of TTv2, revealing that the relative location of the retention convergence point critically determines the available weight range and, consequently, affects the training accuracy. We propose a retention-aware zero-shifting technique designed to optimize neural network training performance, particularly in scenarios involving cross-point devices with limited retention times. This technique ensures robust and efficient analog neural network training despite the practical constraints posed by analog cross-point devices.

Analog in-memory computing, leveraging resistive switching cross-point devices known as resistive processing units (RPUs), offers substantial improvements in the performance and energy efficiency of deep neural network (DNN) training. Among the promising candidates for RPU devices, the capacitor-based synaptic circuit stands out due to its near-ideal switching characteristics. However, despite its potential, challenges such as large cell areas and retention issues remain to be addressed. In this work, we study the three-transistors-one-capacitor synaptic cell design, aiming to enhance computing performance and scalability. Through comprehensive device-level modeling and system-level simulation, assessment is done on how the transistor characteristics influence DNN training accuracy and reveal critical design strategies. A novel cell design methodology that optimizes computing performance while minimizing cell area is proposed, thereby enhancing scalability. Additionally, development guidelines for cell components are provided, identifying oxide-based semiconductors as a promising channel material for transistors. This research contributes valuable insights for the development of future analog DNN training accelerators using capacitor-based synaptic cell, with a focus on addressing the current limitations and maximizing efficiency.

Recently, specialized training algorithms for analog cross‐point array‐based neural network accelerators have been introduced to counteract device non‐idealities such as update asymmetry and cycle‐to‐cycle variation, achieving software‐level performance in neural network training. However, a quantitative analysis of how these algorithms affect the relaxation of device specifications is yet to be conducted. This study provides a detailed analysis by elucidating the device prerequisites for training with the Tiki‐Taka algorithm versions 1 (TTv1) and 2 (TTv2), which leverage the dynamics between multiple arrays to compensate for device non‐idealities. A multiparameter simulation is conducted to assess the impact of device non‐idealities, including asymmetry, retention, number of pulses, and cycle‐to‐cycle variation, on neural network training. Using pattern‐recognition accuracy as a performance metric, the required device specifications for each algorithm are revealed. The results demonstrate that the standard stochastic gradient descent algorithm requires stringent device specifications. Conversely, TTv2 permits more lenient device specifications than the TTv1 across all examined non‐idealities. The analysis provides guidelines for the development, optimization, and utilization of devices for high‐performance neural network training using Tiki‐Taka algorithms.

This work presents an analog neuromorphic synapse device consisting of two oxide semiconductor transistors for high-precision neural networks. One of the two transistors controls the synaptic weight by charging or discharging the storage node, which leads to a conductance change in the other transistor. The programmed weight maintains for more than 300 s as electrons in the storage node are well preserved due to the extremely low off current of the oxide transistor. Ideal synaptic behaviors are achieved by utilizing superior properties of oxide transistors such as a high on/off ratio, low off current, and large-area uniformity. To further improve the synaptic performance, self-assembled monolayer treatment is applied for reducing the transistor conductance. The reduction of on current reduces the power consumption, and the reduced off current improves the retention characteristics. There is no noticeable decrease in simulated neural network accuracy even when the measured device-to-device variation is intentionally increased by 200%, indicating the possibility of large-array operation with the synapse device.

Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

Recent progress in novel non-volatile memory-based synaptic device technologies and their feasibility for matrix-vector multiplication (MVM) has ignited active research on implementing analog neural network training accelerators with resistive crosspoint arrays. While significant performance boost as well as area- and power-efficiency is theoretically predicted, the realization of such analog accelerators is largely limited by non-ideal switching characteristics of crosspoint elements. One of the most performance-limiting non-idealities is the conductance update asymmetry which is known to distort the actual weight change values away from the calculation by error back-propagation and, therefore, significantly deteriorates the neural network training performance. To address this issue by an algorithmic remedy, Tiki-Taka algorithm was proposed and shown to be effective for neural network training with asymmetric devices. However, a systematic analysis to reveal the required asymmetry specification to guarantee the neural network performance has been unexplored. Here, we quantitatively analyze the impact of update asymmetry on the neural network training performance when trained with Tiki-Taka algorithm by exploring the space of asymmetry and hyper-parameters and measuring the classification accuracy. We discover that the update asymmetry level of the auxiliary array affects the way the optimizer takes the importance of previous gradients, whereas that of main array affects the frequency of accepting those gradients. We propose a novel calibration method to find the optimal operating point in terms of device and network parameters. By searching over the hyper-parameter space of Tiki-Taka algorithm using interpolation and Gaussian filtering, we find the optimal hyper-parameters efficiently and reveal the optimal range of asymmetry, namely the asymmetry specification. Finally, we show that the analysis and calibration method be applicable to spiking neural networks.

Conductance variations of resistive random-access memory (RRAM) are significant challenges that hinder the accurate inference of neural network (NN) hardware. In this study, we exploit the read noise of the RRAM as an active computational enabler for implementing probabilistic NN. As electrical characteristics of RRAM are directly related to the properties of conductive filament (CF), we statistically explore read current of TiO x -based RRAM with different forming conditions and explain the results by linking the CF model. In addition, an array mapping scheme to transfer weights to one transistor-one RRAM (1T1R) array is experimentally demonstrated. Through NN simulations, we verify that the probabilistic NN shows promising results on nonlinear classification problem avoiding overconfidence compared with deterministic NN.

Transient electronics, a form of electronic devices that disappear physically after a certain operation time, have attracted considerable interest in the area of bioelectronics. Due to their biodegradability and biocompatibility, bioderived materials have been applied to various kinds of transient electronics. This work presents fully degradable memristors and humidity sensors based on a tyrosine-rich peptide. The memristors exhibit a high on/off ratio (>10(6)), stable endurance (similar to 10(4) s), and analog switching behavior. The humidity sensors show high sensitivity, in which the current changes by 3 orders of magnitude in the relative humidity range of 10-90%. By means of a rapid response and recovery time, the sensors can be used to monitor human respiration in real time. These devices are rapidly dissolvable under physiological conditions within 1 min. These results open up the field of biocompatible multifunctional nanoelectronics toward the development of bio-implantable processors and sensors.