Design consideration for fully integrated continuous-time filters operating at very high frequencies are presented. The OTA was designed in TriQuint's 1 μm GaAs depletion-mode technology; the design considerations include frequency response, linearity, output impedance, tunability, stability of the common-mode output signal, temperature and wire inductances. In order to obtain the highest possible frequency response, the frequency limitations caused by the parasitic parameters are emphasized. As a result, an OTA with 7 GHz -3 dB frequency and very small parasitics, and a filter with 200 MHz cut-off frequency are designed

Power consumption, chip area, feedback loop gain, parasitic capacitance and nonlinearity of three popular common-mode feedback (CMF) circuits used in operational amplifiers are analyzed and compared. One of them is chosen as a candidate for CMF in fully differential operational transconductance amplifiers (OTAs). Three improved versions of this circuit that can be used in an OTA without leading to DC offset caused by the always unavoidable tuning are proposed. Simulation results show that the improved circuits reduce the DC offset from 0.6 V to nearly zero for the whole tuning range

A simply full-differential transductor is presented that achieves, based on cancellation of first and higher order nonlinearities, +/- 0.7% linearity error over a +/- 6.4 V differential input range for +/- 5 V power supplies. Common-mode input signals are cancelled at the output. The transconductance can be tuned at least by a factor 3 and f(-3dB) is 63 MHz for 10-mu-m channel length.

A circuit technique based on two CMOS crosscoupled pairs for realising a linear CMOS transconductor of class AB is presented. Design tradeoffs are discussed and a circuit example is presented. SPICE simulation results show that, for a power supply of +/- 5 V, the linearity error is controlled to +/- 1% over a +/- 3 V input range.

A simple modification is proposed for a popular common-mode feedback circuit used in operational amplifiers, such that it can be used in an operational transconductance amplifier (OTA) without leading to significant DC offset caused by the unavoidable tuning of the OTA. Simulation results show that the improved circuit has nearly zero DC offset for the whole tuning range.<>

Square-difference is a new and very attractive linearisation technique. It has been successfully used to implement large-signal MOS transconductors. A transresistor realised with only two MOS devices using the same technique is presented. A linearity error of less than +or-0.5% for the output swing form supply voltage V/sub SS/ to V/sub DD/ is achieved.<>

Current addition, an approach to the design of linear transconductance elements with a very large linear input range, is explored. Design tradeoffs are discussed and a specific circuit is simulated by SPICE as an example. The results show that for a power supply of ±5 V, the nonlinearity error of the sample circuit is controlled to ±0.3% over a ±3-V input range. OTA (operational transconductance amplifier) parameters such as tuning capability, frequency response, and output impedance are examined. The body effect is considered. A second-order filter is presented as an application

The design of a high-speed, linear, tunable operational transconductance amplifier (OTA) with 1 μm GaAs depletion-mode MESFETs is described. Gain-enhancement techniques are used for obtaining high output impedance. In order to achieve a large tuning range with stable DC bias, a combination of digital and analog tuning is used. Diode-only level-shifting stages and bypass capacitors across the diodes are used to optimize the AC response. Emitter degeneration along with small compensation capacitors are used to achieve less than one percent nonlinearity error within a ±0.4 V input range, and to reduce the total excess phase shift. Applications of the OTA in the GHz range are presented as examples

A description is presented of the high-level and logic synthesis stages in the digital design automation system DIADES. High level design, namely, data path synthesis, and control unit synthesis start from a parallel program graph, the form of description that includes both the control-flow and the data-flow graph. While the data path is allocated and scheduled, the control unit is designed to be composed of either microprogrammed units or finite-state machines. The latter are minimized in two dimensions (states and inputs), assigned and realized in logic. Several logic synthesis procedures, respective to various design styles and methodologies, can be used to design combinational parts of state machines, microprogrammed units, and data path logic

A new logic minimizer designed to generate the exact minimum solutions for multivalued input logic expressions is presented. The advantage of this minimizer is that it generates as few prime implicants as possible. A new algorithm is presented for directly generating essential prime implicants in a time close to that for generating a prime implicant by the ESPRESSO-MV expansion process. The authors discuss how to generate the secondary essential prime implicants in order to avoid setting up a covering table, and they present the corresponding algorithms for noncyclic functions. They also discuss the case in which a covering table should be created for obtaining an exact minimum solution and consider how to use the parallel processing techniques for the best speedup

The concept of a mixed-radix multiple-valued input exclusive sum of products (MRESP) is presented, and some possible circuit realizations for the concept are discussed. The algorithm starts from a Boolean function and generates an approximate MRESP form and the appropriate multioutput circuit. Such circuits can have smaller complexity than the EXOR forms with mixed polarity, the PLAs with decoders, and the networks with two-variable function generators. They are also easily testable.<>