We have developed a SiC-FET-type gas sensor that enables highly sensitive NO detection in high-temperature exhaust gas. The gate of the FET is a gas detection layer consisting of yttria-stabilized zirconia, nickel oxide, and platinum, which are deposited on the SiC substrate. The threshold voltage of the FET depends on the NO concentration. Experimental results demonstrate that the FET-type sensor can detect NO concentration less than 1 ppm, thus meeting the specifications required to satisfy the strict regulations for exhaust gas in the next generation.

A high-programming-throughput three-dimensional (3D) vertical chain-cell-type phase-change memory (VCCPCM) array for a next-generation storage device was fabricated. To increase the number of write cells at one time by reducing resistance of bit and source lines, the VCCPCM array includes plate electrodes and double-gate vertical-chain-selection MOSs with 5-nm-thick poly-Si channels. In addition, CO 2 laser annealing enhances the drivability of a poly-Si cell MOS to 680 μA/μm to suppress energy loss in the cell MOS. In addition to write throughput, erase throughput is increased by erasing memory cells in a “bundle” by channel heating (called “bundle erase”). GeSbTe CVD with high uniformity is also developed.

A three-dimensional (3-D) vertical chain-cell-type phase-change memory (VCCPCM) for next-generation large-capacity storage was developed. The VCCPCM features formation of memory holes in multi-layered stacked gates by using a single mask and a memory array without a selection transistor. As a result of this configuration, the number of process steps for fabricating the VCCPCM is reduced. The excellent scalability of the VCCPCM's new phase-change material makes it possible to reduce the cell size beyond the scaling limit of flash memory. In addition, a poly-silicon selection diode makes it possible to reduce the cell factor to 4F 2 . Consequently, relative cost of the VCCPCM compared to 3-D flash memory is reduced to 0.2.

A phase-change memory (PCM) driven by poly-Si MOS transistors was fabricated. The thin phase-change-material layer deposited directly on the channel silicon layer in the PCM enables low-current reset operation (45 μA) compared to the conventional memory structure. This memory-cell configuration enables both a poly-Si MOS-driven stackable memory array and large degree programming parallelization. A contactless simple cell structure makes it possible to reduce the cell size to 4F2 and the number of process steps. Low cost and gigabyte-per-second programming throughput are thus made possible by this stackable phase-change memory.