This paper presents a MEMS surface micro-machined varactor. The dynamic range of this class of varactors is governed by pull-in instability which is ideally one-third of the initial gap between the two electrodes. This paper presents a simple T varactor, whose pull-in stability and hence its dynamic range are increased by applying two independent voltage sources. We introduce an electromechanical model for the proposed structure, and a full analytic solution to the attached pull in problem. Our varactor has capacitance ratio of 2.43:1.

In this paper, we present a novel scheme for designing and fabricating a base chip, which is an approximation of a pyramid shape, and is not limited by the natural slope of 54.7/spl deg/ obtained with wet anisotropic etching of silicon. The application for such a pyramid shape, in our case, is for a single axis scanning micro mirror. The paper presents the methodology for designing and fabricating a surface with an arbitrary slope, as required by the application. In our case, it is an approximation of a desired very moderate slope. The moderate slope serves as an electrostatic actuator with relatively low operating voltage. On top of the base, we bond a mirror chip that includes the opposite side of the actuator, the reflector of the mirror, the mechanical structure of the mirror and the hinges. We present in this paper the motivation to use a pyramidal shaped base. The design is simple and requires knowledge of etch rates in several crystal planes, which can be easily measured. The fabrication tools and methods used herein are based on wet etching of silicon wafers. There is no need for DRIE processes or SOI wafers.

In this paper, we present a novel scheme for designing and fabricating a single axis scanning micro mirror. The device is the match of two chips using a flip chip bonder. In this paper, we describe mostly the top chip that includes the reflecting surface. The device is very low cost and electrostatically actuated with a relatively low voltage. We present the fabrication process scheme, based on wet etching of silicon wafers. We also present the motivation to use thin wafers, as much as 50 /spl mu/m thick, to reach a resonant frequency of 15-30 kHz, suitable for raster scanners such as retinal scan displays. Finally, we present a preliminary prototype produced by such a process.

A simple kinetic model for the metalorganic chemical vapor deposition growth of ternary III-V and II-VI epilayers denoted by AxC1−xB, is presented. The model yields the relationship between the solid composition x of the epilayer and the gas-phase concentrations of the constituents in various limiting cases. The solid composition x is given by x=(1+α−1×CGMC/CGMA)−1 =[1+α−1(1−Z−1)]−1 where α is a fitting parameter determined by the process parameters, CGMA and CGMC are the gas-phase concentrations of the metalorganic sources of A and C, respectively. The gas-phase composition Z is defined by Z=CGMA/(CGMA +CGMC). The predictions of the model are compared with measured data. The data points are calculated with one fitting parameter α, indicating the validity of the model.

1/f noise currents have been measured in HgCdTe photodiodes and gate-controlled diodes as a function of gate bias, diode voltage, and dark (leakage) currents. The diodes are fabricated by ion implanting boron (n+) on bulk p-type material with x=0.22. Native anodic sulfide in combination with deposited ZnS is used for surface passivation. The measurements demonstrate that the dominant mechanism that produces 1/f noise in HgCdTe photodiodes is tunneling. With the gated diodes it is possible to separate bulk and surface related mechanisms responsible for the 1/f noise currents. 1/f noise currents are produced by surface-induced tunneling at pinched-off depletion regions adjacent to accumulated surfaces and by tunneling across field-induced junctions underneath inverted surfaces. Bulk trap-assisted tunneling that limits the R0A product below 50 K but is masked by diffusion at 77 K, is responsible for the 1/f noise currents at optimized surface potentials, (i.e., approximately flat-band conditions) at low bias voltages. For nonoptimized surface potentials, the tunneling currents are either band to band or trap assisted, depending on material properties. The noise associated with band to band tunneling is modeled with In=αt(It)1/2( f )−1/2 where It is the measured tunneling current. The proportionality factor αt between the noise current and the tunneling current in gate-controlled devices is in the range αt=4×10−7√A to αt=1×10−8√A. HgCdTe photodiodes with the same passivation technology but without a gate, fabricated in higher-quality bulk material, operating at high reverse bias, yield αt values that range between αt=2×10−7√A for small area diodes (junction area equals to 6×10−5 cm2) to αt=6×10−8√A for large area diodes (with junctions area equal to 1.45×10−3 cm2). The noise associated with trap-assisted tunneling is modeled with In=αt(It)β( f )−1/2 where β is approximately 0.75. The numerical values of αt are strongly dependent upon material properties and the dimensions are (A)1−β.

The practical aspects of HgCdTe surface passivation, as related to devices and applications, are reviewed. Currently used technologies are classified in two categories: thick deposited dielectrics and a two-layer combination of a thin native film with a thick deposited dielectric film. The first category includes ZnS, low-temperature photochemical vapor deposited SiO2 (photox), and electron cyclotron resonance plasma deposited SiNx. The second category includes anodic oxide, plasma oxide, photochemical native oxide, anodic sulfide, and anodic fluorides. The unique behavior of HgCdTe surfaces, metal-insulator semicoductor structures, and gate-controlled p–n junctions are reviewed. The surface requirements of HgCdTe devices of interest for present and next-generation focal plane arrays are discussed in terms of the reviewed technologies.

The transient and steady-state excess carrier lifetimes in p-type Hg0.775Cd0.225Te have been measured as a function of temperature. It is demonstrated that the transient lifetime can be greater than the steady-state lifetime by as much as a factor of 16 at 77 K. This difference is attributed to minority-carrier trapping, and explains, in part, the large range of lifetimes which have been reported for this material.

Views Icon Views Article contents Figures & tables Video Audio Supplementary Data Peer Review Share Icon Share Twitter Facebook Reddit LinkedIn Tools Icon Tools Reprints and Permissions Cite Icon Cite Search Site Citation Y. Nemirovsky, I. Bloom; Admittance measurements of metal–insulator–semiconductor devices in p‐type HgCdTe. J. Vac. Sci. Technol. A 1 July 1988; 6 (4): 2710–2715. https://doi.org/10.1116/1.575491 Download citation file: Ris (Zotero) Reference Manager EasyBib Bookends Mendeley Papers EndNote RefWorks BibTex toolbar search Search Dropdown Menu toolbar search search input Search input auto suggest filter your search All ContentAVS: Science & Technology of Materials Interfaces and ProcessingJournal of Vacuum Science & Technology A Search Advanced Search |Citation Search

A novel set-up for horizontal open-tube vapor transport epitaxy of HgCdTe films is described. Mirror-like HgCdTe epitaxial layers with thicknesses up to 40 Μm were grown and characterized. The growth temperature ranged from 380 to 550‡C, with growth rates of the order of 0.5–7 Μm per hour. The concentration depth profiles and the optical and electrical properties of relatively uniform films with x≈0.3–0.4 are reported. The process kinetics are studied. A simple model which takes into account the reactions occurring at the boundaries of the epitaxial layer and the interdiffusion in the epilayer is presented and discussed. The model fits the experimentally observed characteristics of the epitaxial growth process. A constant growth rate leading to a linear dependence of film thickness upon deposition time y–y=k t is derived. The reaction rate constant k is given by k=kea with k=0.18 cm-secand the energy of activation E=1.12 eV.

The results of galvanomagnetic measurements in N-type Hg1−xCdxTe, as a function of magnetic field for the compositions x≃0.215 and x≃0.29 and over the temperature range 15⩽T⩽300 K are reported. A unified model is proposed which fits the magnetic field dependence of both the conductivity and the Hall coefficient. The most significant feature of the model is that two types of electrons are contributing to the transport properties and are responsible for the magnetic field dependence of the conductivity and the Hall coefficient. The two sets of electrons have mobilities which at the lowest measured temperature (15 K) differ by up to two orders of magnitude, and have concentrations which are of the same order of magnitude.

The electrical properties of P and B implanted and cw CO2 laser annealed n- and p-type Hg1−x CdxTe (x=0.21, 0.29) are studied. Hall, conductivity, and capacitance-voltage (C-V) measurements carried out on the virgin, implanted, and annealed samples all show that both donor and acceptor implants can be electrically activated when annealing with a cw CO2 laser (0.3 s, 250 W/cm2) is employed.

AbstractAnwendung von Iz‐haltigen Ätzlösungen auf auf Cr‐Adhäsionsschichten abgeschiedene Au‐Filme führt zur Ausbildun von Hohlräumen an der Filmbasis.