A technique for trading off the main lobe width against sidelobe magnitude for any arbitrary window was reported in Lim et al. and subsequently, a fast convergence method for its implementation was proposed by the same authors. These methods require the computation of derivatives involving the evaluation of trigonometric and hyperbolic functions. In this paper, we show that the derivatives can be computed without evaluating trigonometric and hyperbolic functions if the window function is a sum of exponentials such as a Fourier series.

A very efficient technique for significantly reducing the number of multipliers and adders in implementing narrow transition band linear-phase finite-impulse response (FIR) digital filters is to use the frequency-response masking (FRM) approach. This paper studies the construction of the masking filter pair in the FRM technique using a common part for further reducing the arithmetic complexity. Extensive simulations are included showing that the use of the common part always considerably decreases the arithmetic complexity at the expense of a slight increase in the overall filter order.

The frequency-response masking (FRM) filters can achieve arbitrary delay if all of the subfilters are nonlinear phase finite impulse response (FIR) filters. However, its arithmetic complexity is inevitably increased. In this paper, we propose a three-stage method to increase the number of zero-valued coefficients. In Stage I and Stage II of our approach, the l(1)-norm of the coefficient values is included as a component of the objective function to be minimized. Simulation results show that the proposed method produces arbitrary delay FRM filters with significantly reduced arithmetic complexity compared to the method without optimizing the sparsity.

IIR frequency-response masking (FRM) filter where the prototype filter is an IIR filter and the masking filters are FIR filters is effective in reducing the group delay of FRM filters. In this paper, we present a constrained optimization method for the design of near linear phase IIR FRM filters, where the phase error and magnitude error are independently controlled. A design example is presented to demonstrate the performance of the method.

Time-interleaved analog-to-digital converter (TIADC) mismatch compensation filters are traditionally finite impulse response (FIR) filters. The advantages of using FIR filters are that FIR filters are inherently stable and that the design techniques are readily available. This paper demonstrates that infinite impulse response (IIR) filters can be designed to compensate for the mismatch error in the TIADC. Two methods for achieving stability are introduced; one is by increasing the group delay and the other is by constraining the magnitudes of the denominator coefficients. Simulation examples show that, for a given spurious frequency power, the proposed IIR TIADC compensation filter yields about 30% saving in the total number of multiplier coefficients when compared to the conventional FIR TIADC compensation filter. Important aspects of the IIR compensation filter such as noise propagation, performance in the presence of identification error, filter redesign to cope with mismatch drifting are also investigated.

In this paper, we have presented a detailed analysis of pole position approximation for pilot notches to understand its overall effect on steering direction determination and convergence of the notch filter. We have introduced an improved piloted adaptive notch filter with transient suppression and a higher probability of correct steering direction. The concept of variable pole-radius has been employed to significantly reduce the transient effect and improving the directional properties of the notch. Computer simulations demonstrate the excellent performance of the variable-pole radius piloted notch filter to significantly outperform the traditional piloted notch filter with respect to the speed of convergence and steady-state mean square error (MSE).

In this paper, we have proposed a new steering direction determination mechanism and step-size update algorithm for piloted adaptive notch filter architecture. A time-domain averaging based gradient analysis of the piloted notch cost function has been utilized to determine the direction of the main notch with respect to the input sinusoid frequency. The steering direction will indicate the distance between the frequency of the input sinusoid and the zero of the main notch. This frequency domain information has been interleaved with time domain information to develop a novel algorithm for determination of variable step-sizes for improved speed of convergence with comparatively huge reduction in steady-state mean square error (MSE). The simulation results verifies the excellent performance exhibited by our proposed steering mechanism and the step-size update algorithm over original piloted adaptive notch filter with respect to the speed of convergence and MSE.

In this paper, we have presented a multi-piloted notch filter structure with the generalized formulation for introduction of more number of pilots to the original piloted notch filter having an option for a range of step-size values. The structure of multi-piloted notch filter has been studied through simulations to make it more adaptive by using multiple step-size values. Thus, the transition from a very large step-size value to a very small step-size value has been smoothed using intermediate values of step-size such that the main notch does not cross-over the frequency of input sinusoid with larger error when it is very close to it. Moreover, this has been useful in selecting a larger step-size value when the notch is away from the input frequency to increase the rate of convergence. The simulation results verify the excellent performance exhibited by multi-piloted notch filter over the original piloted notch filter with respect to the speed of convergence and mean square error (MSE).

June 16, 2015 12: 59 PSP Book-9in x 6in 01-Yong-Ching-Lim-c01

The excellent finite wordlength (FWL) property of lattice digital filters is well known. The four-multiplier normalized lattice, with signal power at all delay elements normalized to unity, has particular advantage in its overflow property. However, when used to implement an Nth-order digital filter, the normalized lattice implementation requires 5N+1 multipliers. There exists another lattice structure with excellent FWL property called the injected numerator lattice structure. In this paper, we combine the injected numerator lattice and tapped numerator lattice to form a new hybrid lattice structure, which is not only canonic in the number of multipliers resulting in a significant reduction in overall implementation cost but also exhibits much better FWL properties than the normalized lattice structure. An improved “peakedness” measure is also introduced for application where the input signal has a strong time varying sinusoidal component. The new structure requires a few additional adders; it can be used to implement any causal and stable z-transform transfer function. Two numerical examples are presented to demonstrate the performance of the proposed structure.

In this paper, we have presented the performance comparison of the piloted adaptive notch filter with the second-order adaptive IIR lattice notch filter and the adaptive IIR notch filter with constrained poles and zeroes. The steady-state analysis for mean square error (MSE) of the frequency estimate using simulations has been provided with roles of the user variables such as notch bandwidth and signal to noise ratio (SNR). This study verifies the excellent performance exhibited by the piloted adaptive notch filter over other algorithms with respect to the speed of convergence and MSE. Extensive computer simulations have been done to study the performance over a wide range of SNR and frequency values.

Time interleaving is an effective method for increasing the sampling rate of electronic analog-to-digital converters (ADCs). The main artifact of time-interleaved ADC (TI-ADC) is caused by mismatches between different sub-ADC channels. The mismatches include mismatches in gain, bandwidth, and frequency response. The ultimate achievable bandwidth of the TI-ADC is limited by the bandwidth of the sample-and-hold (S/H). Currently, the bandwidth of S/H constructed using electronic transistor is limited to the lower tens of GHz range. To increase the bandwidth of ADC into the upper tens of GHz range and beyond, incorporating photonic preprocessor becomes the natural choice. In this paper, we present our efforts on the implementation of a massively parallel TI-ADC with photonic preprocessor. In our system, the input signal is sampled using a mode-lock laser. The sampled pulses are stretched in optical fiber until they are long enough to be sampled by a massive array of 2 Giga-samples per second (GS/s) electronic ADC.

This paper presents an approach for digital lattice filter roundoff noise reduction using error spectrum shaping (ESS). ESS roundoff noise expression for the one-, two-, three-, and four-multiplier lattice structures are derived. A numerical example for demonstrating the performance of the proposed ESS noise reduction in lattice filters is also presented.

Most of the existing design methods for digital filters that are to be implemented with finite precision device are given by two independent stages. The first stage is to determine a transfer function (in infinite precision) that meets the specifications given, while the second one is to choose a proper filter structure to reduce finite wordlength (FWL) errors as much as possible. In this paper, we propose a new digital filter design strategy that merges the two stages such that both the performance and the structure issue are considered simultaneously with the FWL effects taken into account. The idea is developed with a recently proposed lattice-based filter structure [8]. A design example is given, which shows that the obtained structure-based filter not only outperforms existing lattice-based filters in terms of reducing the FWL effects but also has a much lower implementation complexity than the latter and the canonical filter realizations.

In this paper, the timing mismatch compensation problem in the implementation of a time-interleaved analog-to-digital converter (TIADC) is investigated. The investigation leads to a novel multichannel Lagrange polynomial interpolation timing-mismatch compensation algorithm (MLPI-TMCA). A multichannel Lagrange compensation filter (MLCF) in the form of a finite-impulse response (FIR) filter is also developed for real-time implementation. The design of the compensation system is done in three steps. First, the coefficients of the MLCF are computed based on the mismatch parameters of the TIADC. Second, an N th order FIR filtering process is performed for each sub-ADC. Third, a multiplexer is used to combine the output of each compensation filter in an orderly manner into the final compensated output signal. The computational complexity of this timing mismatch compensation system is of order N . Computer simulation results showed that MLPI-TMCA is computationally efficient and not sensitive to timing mismatch fluctuations. The actual implementation of a four-channel 320-MHz 12-bit TIADC showed that the MLPI-TMCA is able to efficiently compensate the timing mismatch in a real-time manner and produced about 30-dB spurious-free dynamic range (SFDR) enhancement when the input signal frequency is 70 MHz, whereas the multirate filter banks compensation method produced about 19 dB of SFDR enhancement under the same condition. Thus, the MLPI-TMCA and its multichannel filter implementation provides a good solution for TIADC real-time timing mismatch compensation and may be employed in TIADC chip design due to its implementation advantages.

This paper proposes an efficient structure for implementing a linear-phase finite-impulse-response (FIR) filter of an arbitrary order $N$ for the sampling-rate conversion by a rational factor of $L/M$ , where $L(M)$ is the integer upsampling (downsampling) factor to be performed before (after) the actual filter. In this implementation, the coefficient symmetry of the linear-phase filter is exploited as much as possible and the number of delay elements is kept as low as possible while utilizing the following facts. When increasing (decreasing) the sampling rate by a factor of $L(M)$ , only every $L$ th input sample has a nonzero value (only every $M$ th output sample has to be evaluated). In this way, the number of required multiplications per output sample is reduced approximately by a factor of two compared with the conventional polyphase implementation. The proposed implementation is first illustrated using two examples. Based on these examples, guidelines are then given on how to efficiently realize an $N$ th-order linear-phase FIR filter for a sampling-rate converter having an arbitrary rational conversion factor $L/M$ . Finally, the implementation complexity of the proposed approach is evaluated and some examples are included, showing the efficiency of the proposed implementation compared with other existing ones.