Adopting LLW DRAM in modern mobile systems has increased vulnerability to RowHammer attacks due to shorter row cycle times. This paper introduces LLW Line Encrypted Aggressor Pinning (LEAP), a high-security, high-performance, low-power in-DRAM RowHammer mitigation scheme for LLW DRAM systems. It features line-level address encryption and data pinning, aligning with LLW's characteristics, and enhances performance by 2.4% while reducing power consumption by 6.8% compared to traditional victim refresh methods.

Contemporary data center CPUs are experiencing an unprecedented surge in core count. This trend necessitates scrutinized Last-Level Cache (LLC) strategies to accommodate increasing capacity demands. While DRAM offers significant capacity, using it as a cache poses challenges related to latency and energy. This paper introduces Native DRAM Cache (NDC), a novel DRAM architecture specifically designed to operate as a cache. NDC features innovative approaches, such as conducting tag matching and way selection within a DRAM subarray and repurposing existing precharge transistors for tag matching. These innovations facilitate Caching-In-Memory (CIM) and enable NDC to serve as a high-capacity LLC with high set-associativity, low-latency, high-throughput, and low-energy. Our evaluation demonstrates that NDC significantly outperforms state-of-the-art DRAM cache solutions, enhancing performance by 2.8%/52.5%/44.2% (up to 8.4%/140.6%/85.5%) in SPEC/NPB/GAP benchmark suites, respectively.

This article proposes practical design techniques to enhance performance and reliability of 1024 GB/s high-bandwidth memory-3 (HBM3). Effective data-bus design methods are applied to transfer data from multi-bank to a data-bus with a sufficient data fetch margin. A symbol-based on-die error-correcting code (OD-ECC) to correct a 16-bit error, bounded by a sub-wordline (WL), and parallelized data-bus inversion (DBI) are implemented. Error check and scrub (ECS) mode and repair capability check (RCC) mode with an internal serial interface are designed to support system reliability, availability, and serviceability (RAS). A memory built-in self-test (MBIST) provides a unified at-speed test with programmability based on test-set units (TUs). A 16 GB HBM3 fabricated in the third generation of the 10 nm class DRAM process achieves a bandwidth up to 1024 GB/s (8 Gb/s/pin) and provides stable operation at a high temperature (e.g., 105 °C) while improving an error detection rate by 92.2%.

This paper presents the symbol-based On-die ECC (OD-ECC) configuration of High Bandwidth Memory-3 (HBM3) to correct a 16-bit error, bounded by a sub-wordline (WL), and implementation for parallelized data bus inversion (DBI). In addition, the die-to-die integration method for error check and scrub (ECS) mode, and programmable memory built-in self-test (MBIST) design approach for at-speed test are de-scribed. The fabricated HBM3 improves the error detection rate by 92.2% with 99.7% fault coverage of OD-ECC logic while achieving 8.0 Gb/s/pin.

Circuit and design techniques are presented for enhancing the performance and reliability of a 3-D-stacked high bandwidth memory-2 extension (HBM2E). A data-bus window extension technique is implemented to cope with reduced clock cycle time ranging from data-path architecture, through-silicon via (TSV) placement, and TSV-PHY alignment. A power TSV placement in the middle of array and at the chip edge along with a dedicated top metal for power mesh improves power IR drop by 62%. An on-die ECC (OD-ECC) scheme featuring a self-scrubbing function is designed to be orthogonal to system ECC. An uncorrectable bit error rate (UBER) is improved by 10 5 times with the proposed OD-ECC and scrubbing scheme. A memory built-in self-test (MBIST) block supports low-frequency cell and core test in a parallel manner and all channel at-speed operation with adjustable ac parameters. The proposed parallel-bit MBIST reduces test time by 66%. A 16-GB HBM2E fabricated in the second generation of 10-nm class DRAM process achieves a bandwidth up to 640 GB/s (5 Gb/s/pin) and provides a stable bit-cell operation at a high temperature (e.g., 105 ° C).

HBM3 is the next-generation technology in the JEDEC High Bandwidth Memory™ die-stacked DRAM standard. HBM3 is expected to be widely used in future SoCs to accelerate data center and automotive workloads. Reliability, Availability, and Serviceability (RAS) are key requirements in most of these computing domains and use cases. Memory reliability is especially key to attaining resilience at scale. This paper presents the RAS challenges facing HBM3 and how they are addressed by a novel memory RAS architecture that is now part of the HBM3 standard. The paper shows how this novel HBM3 RAS architecture can reduce the uncorrected memory error rate by 7X compared to HBM2 in future large-scale systems for assumed DRAM fault rates and modes . HBM3 also provides architected metadata to further enhance RAS or enable innovations in memory system design.

Rapidly evolving artificial intelligence (Al) technology, such as deep learning, has been successfully deployed in various applications: such as image recognition, health care, and autonomous driving. Such rapid evolution and successful deployment of Al technology have been possible owing to the emergence of accelerators, such as GPUs and TPUs, that have a higher data throughput. This, in turn, requires an enhanced memory system with large capacity and high bandwidth [1]; HBM has been the most preferred high-bandwidth memory technology due to its high-speed and low-power characteristics, and 1024 IOs facilitated by 2.5D silicon interposer technology, as well as large capacity realized by through-silicon via (TSV) stack technology [2]. Previous-generation HBM2 supports 8GB capacity with a stack of 8 DRAM dies (i.e., 8-high stack) and 341GB/s (2.7Gb/s/pin) bandwidth [3]. The HBM industry trend has been a speed improvement of 15~20% every year, while capacity increases by 1.5-2x every two years. In this paper, we present a 16GB HBM2E with circuit and design techniques to increase its bandwidth up to 640GB/s (5Gb/s/pin), while providing stable bit-cell operation in the 2 nd generation of a 10nm DRAM process: featuring (1) a data-bus window-extension technique to cope with reduced $t_{cco}$ , (2) a power delivery network (PDN) designed for stable operation at a high speed, (3) a synergetic on-die ECC scheme to reliably provide large capacity, and (4) an MBIST solution to efficiently test large capacity memory at a high speed.

High-density and high-speed DRAM requirements have been ever-increasing to achieve a better user experience for mobile systems, by adopting QHD (2560×1440), and higher display resolutions, dual cameras, augmented reality, and advanced driver-assistance systems. LPDDR4X has been the hand-held and mobile memory of choice due to its high speed (5.0Gb/s/pin [1]) and low-power data retention (<0.1mW/Gb [2-3]), as well as reliability due to in-DRAM ECC. The DRAM process continues to scale down to the 10nm era to meet the ever increasing density requirements (LPDDR4X density doubles every two years for flagship smart-phones). However, poor data retention characteristics due to smaller storage capacitances and device issues, such as reliability (NBTI) and leakage (especially core transistors), with the traditional poly-gate and planarbulk technology becomes a primary concern for mobile DRAM. In-DRAM ECC is fully supported by the JEDEC LPDDR4 specification by the introduction of the new masked-write command (MWR; f CCDMW =32f CK ), however the area overhead (6.25%), due to the additional parity arrays for a (136, 128) single-error-correction code [4], is currently limiting for mass production in terms of chip cost. This overhead can be mitigated by adopting a scaled technology node that enables a smaller chip size as well as better retention time due to ECC. This paper presents several circuit techniques to maintain LPDDR4X's high speed and low power in a 10nm class process, thereby enabling a cost-effective DRAM design with inDRAM ECC: using (1) an NBTI-tolerant circuit solution that covers whole high-speed circuit regions, (2) a sub-WL driver (SWD) PMOS GIDL-reduction technique ensures stable power recovery, (3) an adaptive IO buffer current gear-down scheme based on user-scenarios, and (4) a metastable-free DQS aligner. Figure 12.2.1 shows the top-level block diagram of the 8Gb/1channel macro, with an in-DRAM ECC using a (136, 128) single-error-correction code, similar to that of previous 20nm designs [2-4].