This paper addresses the problem of maximizing the apa ity of multi hannel Slotted ALOHA networks subje t to a deadline and a permissible probability of ex eeding it. A previous paper proposed to transmit a non-de reasing number of opies of a message in su essive rounds until su ess or deadline. This yielded a low probability of failure due to the large maximum number of opies per message, with only minimal \pollution" due to the small mean number of opies. In this paper, we examine another way of implementing variable resour e expenditure in di erent rounds: the hannels are partitioned into groups, one for ea h round (until the deadline), and the hannels used by later rounds are operated with lower o ered loads. These Multiple Working Point (MWP) poli ies are shown to attain a lower apa ity than the optimal Multi opy (MC) s heme. Combining the two to form an MC-MWP s heme slightly improves apa ity over MC-SWP. The SCMWP approa h an be more attra tive when using a single transmitter per station be ause, unlike MC, transmission time is not prolonged. Therefore, as the trend from high orbit satellites to networks with lower propagation delays ontinues, Multiple Working Point poli ies should be ome of more interest.

Analyses and simulations have shown that interconnect shielding can replace a large fraction of the delay buffers used to achieve timing goals through a useful skew clock design methodology. Immunity from process, operation, and environmental variations in nanoscale CMOS technology clock designs are essential, thus making predictable delays and useful skews highly important. We examine interconnect shielding intradie within-die (WID) and interdie die-to-die (D2D) variations under a wide variety of (P, V, T) corners, and show their applicability and ability to achieve clock design timing goals. The analysis is based on post-silicon measurements of a novel shielded interconnect ring oscillator in a 16-nm test chip supported by a rigorous provable estimation methodology.

We present the architecture and design of a novel 64 x 64 CMOS single-photon avalanche diode (SPAD)-based imager for gun muzzle flash detection. The imager is fabricated in a standard front side illuminated 0.18 mu m CMOS image sensor process. Each pixel comprises a 25 mu m diameter SPAD, a variable-load passive quenching circuit implemented with 1.8 V PMOS, an 8-bit counter, an 8-bit latch register, and digital processing electronics, and feeds an 8-bit output bus. The array delivers two-dimensional intensity data through photon counting, with integration time as low as 5 mu s over the full dynamic range. Per-pixel digital memory enables fully parallel processing and global-shutter mode readout. The imager can acquire fast optical events at high frame rate (up to 200 kfps) and at single-photon sensitivity. The imager has an 8-pixel (64-bit) parallel output bus. This imager enables for the first time the detection and arrival-direction determination of individual muzzle flashes in real time, and even in the case of bursts of flashes, at a moderate cost and size. The presented results confirm the feasibility of gun muzzle flash online detection in the visible or NIR spectrum by uncooled silicon SPAD detectors using standard CMOS technology.

In this work we present the Secure Machine, SeM for short, a CPU architecture extension for secure computing. SeM uses a small amount of in-chip additional hardware that monitors key communication channels inside the CPU chip, and only acts when required. SeM provides confidentiality and integrity for a secure program without trusting the platform software or any off-chip hardware. SeM supports existing binaries of single- and multi-threaded applications running on single- or multi-core, multi-CPU. The performance reduction caused by it is only few percent, most of which is due to the memory encryption layer that is commonly used in many secure architectures. We also developed SeM-Prepare, a software tool that automatically instruments existing applications (binaries) with additional instructions so they can be securely executed on our architecture without requiring any programming efforts or the availability of the desired program`s source code. To enable secure data sharing in shared memory environments, we developed Secure Distributed Shared Memory (SDSM), an efficient (time and memory) algorithm for allowing thousands of compute nodes to share data securely while running on an untrusted computing environment. SDSM shows a negligible reduction in performance, and it requires negligible and hardware resources. We developed Distributed Memory Integrity Trees, a method for enhancing single node integrity trees for preserving the integrity of a distributed application running on an untrusted computing environment. We show that our method is applicable to existing single node integrity trees such as Merkle Tree, Bonsai Merkle Tree, and Intel`s SGX memory integrity engine. All these building blocks may be used together to form a practical secure system, and some can be used in conjunction with other secure systems.

RotorNet comprises switches that provide direct all-to-all connectivity among data-center nodes by cycling among all cyclic shift permutations. Combined with two-hop routing, whereby packets traverse the optical network twice, they provide high throughput regardless of the traffic pattern and with no need for centralized control. Although being a circuit-switched optical interconnect intended primarily for latency-insensitive traffic, reducing latency saves energy and buffer space, and is thus important. We show that latency can be reduced by properly timing the transmissions by the sender, and offer insights along with some useful results.

Shielding, which is used in VLSI designs to prevent noise interference from the cross-coupling capacitance between adjacent signals can also he used to tune the propagation delay of the clock signals in designs operating at low GHz frequencies. This paper presents a detailed design for a 16-nm ring oscillator with built-in reconfigurable shielding, and a delay estimation methodology. Together these provide a post-silicon measurement methodology that can derive accurate shielding delays without any direct delay measurements. The shielded ring oscillator and the testing methodology are designed to minimize the effects of on-die variations on estimation accuracy. Comparisons of the estimated delays with SPICE simulations show very good fit across process technology corners. The circuit was fabricated in 16-nm technology. The accuracy and robustness of the estimation methodology were verified by cross-validation, obtained from both pre and post-silicon measurements.

Redundancy is widely used for fault tolerance: storing multiple copies of data, executing the same instructions on multiple processors, providing alternate paths in a communication network, etc. However, redundancy can also be used for improving performance and even cost-performance. In some cases, combining it with randomization is highly beneficial: randomization makes performance insensitive to specific scenarios (e.g., balances average load), and redundancy is used to handle the rare “bad” cases. Moreover, this approach often results in the ideal combination of “selfish” policies with “good citizenship”. We illustrate this using examples from our own past research, and offer important insights. The ideas are applicable to numerous fields.

We present the architecture and design of a CMOS single-photon avalanche diode (SPAD) pixel that was selected to be the basis for a gun muzzle flash detection camera. The SPAD sensor and auxiliary circuitry are fabricated in a standard 0.18-mu m CMOS image sensor technology. The pixel integrates a 25-mu m pitch SPAD, a variable-load quenching circuit implemented with a 1.8-V pMOS, and digital processing electronics providing an 8-bit output bus. The SPAD is low noise (around 100-Hz dark count rate at 1.8-V excess voltage) and has a real peak photon detection efficiency (not averaged on pixel pitch) of 9.2% at 450 nm (1.8-V excess voltage). The pixel delivers intensity information through photon counting, up to 256 counts per frame with down to 5-mu s integration time for the full dynamic range. The pixel memories enable parallel processing and global-shutter readout, preventing motion artifacts and partial exposure effects. The pixel can acquire very fast optical events at a high frame-rate (up to 200 kilo frames/s) and at a single-photon level. The pixel has an 8-bit parallel output bus.

Rotor Switches are optical switches that provide cyclic-shift permutations with a fixed round-robin schedule. They have been shown to offer high throughput while significantly reducing control complexity, making them a promising candidate for use in optical data center interconnects. We successfully address two critical challenges impeding the adoption of such circuit switched data center interconnects: 1) switch scalability, and 2) support for simultaneous 2-way connectivity to enable using low-latency protocols.

Ensuring the correct execution of a program running on untrusted computing platforms, wherein the OS, hypervisor, and all off-CPU-chip hardware, including memory, are untrusted, (also) requires protecting the integrity of the memory content against replay attacks. This requires dedicated tracking structures and in-chip state storage. For this purpose, integrity trees are used in various forms, varying in complexity, size, and performance; yet, existing integrity trees do not address distributed, shared-memory computations, for which one must also ensure the integrity of the coherence state of the memory. Observing that a block not residing at a given node merely needs to be known by that node as such, we present the novel Distributed Integrity Tree (DIT) method, and show that it can be used effectively to extend existing integrity trees to parallel and distributed environments. Using DIT, we constructed a Distributed Merkle Tree, a Distributed Bonsai Merkle Tree, and a distributed Intel SGX's Memory Encryption Engine integrity mechanism. All these extensions entail negligible overhead.

Computer malware is one of the greatest dangers to the modern society, allowing attackers to uncover restricted data and to control a wide range of critical infrastructure. Furthermore, computer malware evolve rapidly, forcing anti-malware vendors to put most of their efforts on developing techniques for detecting new and therefore previously unknown malware. We present Split Malware, a method for splitting malware into small pieces. Each piece is not discovered by anti-malware tools, yet together they perform a malicious task.

Fast switching and accurate timing are deemed desirable, but may come at a cost, restrict technology choices, etc. In the context of a hybrid data center network, we point out dependencies among speed, various times and even energy, provide insights and offer some guidelines.

In shared (multi-user) computing environments, platform software (OS, Hypervisor, VMM etc.) and most of the hardware cannot always be trusted (e.g., public clouds), so ensuring the confidentiality and integrity of a user's program (code and data) is critical. It is highly desirable to do so efficiently while accepting existing application binaries, being able to use the services of untrusted software, not modifying the OS, and with minimal intervention in the system's flow. We present the Secure Machine (SeM), a CPU architecture extension that, unlike previous approaches, does all this. Using novel fine-grained cache and register protection managed by a CPU-resident, publicly identifiable hardware Security Management Unit (SMU), we address both software attacks and off-chip hardware attacks. SeM accepts existing application binaries, which are instrumented automatically, and only incurs negligible performance, power, and area overheads relative to an unprotected platform. SeM is extendable to parallel programs and multiple nodes.

In just 3 FPGAs we realize fastest (180 Gbps) real-time filter-bank based DFT-S CO-OFDM 16-QAM 25 GHz Rx, at record 1.06 samples/symbol (7.3 b/Hz), demonstrating dual polarization SMF transmission. Extrapolated ASIC would save <50% power. Introduction Coherent optical orthogonal frequency division multiplexing (CO-OFDM), including Discrete Fourier Transform -spread (DFTS-OFDM) variants [1,2] with dual-polarization QAM is a promising technology for optical communication. In recent years, several groups demonstrated real-time high-speed CO-OFDM implementations. For practical systems, overall complexity must be reduced and efficiency be improved. In this work we report the fastest and the most efficient realtime receiver (Rx) system, based on our novel sub-banding DFTS-OFDM DSP(Tab.1) [2, 3]. This work takes a major step toward more efficient hardware (HW) implementation with higher spectral efficiency and lower sampling rates and significant reduced HW-computational complexity of the receiver (Rx) – as itemized in the note above. Our demonstrated shorter reach is not an actual system limitation but is due to experimental resource availability. In fact, our attained EVM in principle suffices for competitive extrapolation of distances. Our key advantages: (i) major reduction (~ factor-of-two) in the real-time HW requirement, attained due to our unique twice-under-decimated digital sub-banding technique theoretically detailed in [2]; (ii) maximizing spectral efficiency (SE) and reducing sampling rate to 1.07 samples/symbol (rather than conventional 2 samples/symbol) due to unique digital subbanding algorithm [2] eliminating spectral guardbands between the sub-bands, e.g. as in [7]. (iii) First real-time highly HW-efficient FPGA implementation of specific novel DSP algorithms (at the sub-band processor level): GolayComplementary-Codes (GCC) based timing recovery and Pilot-assisted Carrier Frequency Offset (CFO) compensation, where the pilot resides in the mid sub-band, saving HWexpensive band-pass-filtering. System description The experimental setup (Fig. 1) comprises an optical transmitter (Tx) and Rx for 180 Gbps data Tab. 1: Some recent CO-OFDM real-time demonstrations in comparison with our current work Author[Ref.] Net Rate Baud Rate DAC/ADC HW Platform Modulation Spectral Efficiency Distance S. Chen [4] 110Gbps 18GBd 6G/1.5G 1 FPGA chip DP-QPSK 1.9 bit/Hz 600km N.Kaneda [5] 76Gbps 29GBd 64G/32G 4 FPGAs Virtex-7 DP-QPSK 2.9 bit/Hz 500km X. Xiao [6] 100Gbps 16.3GBd 63G/ 42G 32 FPGAs Virtex-6 DP-16QAM 6.57bit/Hz 200km This Work 180Gbps 25GBd 26.6/26.6G 3 FPGAs* Virtex-6 DP-16QAM 7.3bit/Hz 100km *Note: Our system needs just 3 FPGAs to arbitrarily access on the fly in real-time, any of the 14 data-carrying sub-bands per channel. Extrapolated to a full Rx serving all 15 sub-bands of the 25 GHz channel, the equivalent processing power of 16 Virtex-6 FPGA would be required to process all sub-bands in parallel; still our full extrapolated system would remarkably require a factor-of-two fewer FPGAs than that state-of-the-art demo of Xiao [6], yet our system carries almost twice the bit rate (180 Gbps rather than 100 Gbps in [6]). Fig. 1: (left) System block diagram of experimental setup. (right) Real-time 180 Gbps sub-banded DFT-S OFDM Rx on just 3 Virtex6 FPGAs 388 ECOC 2016 42nd European Conference and Exhibition on Optical Communications September 18 – 22, 2016 Düsseldorf ISBN 978-3-8007-4274-5 © VDE VERLAG GMBH Berlin Offenbach payload over a 100Km SMF optical link. At the Tx side, each transmission band is digitally multiplexed out of 16 Single Carrier (SC) subbands, realized as DFTS-OFDM 16-QAM per sub-band modulation (Fig. 2). Among the 16 subbands, 14 of them carry uncorrelated PRBS19 data; two sub-bands do not carry data but are reserved for special purposes: the 16th wrapped around sub-band provides ADC anti-aliasing filter transition; the 8th sub-band carries two ±415.6 MHz pilots for CFO/phase recovery. The 14 remaining sub-bands carry data, 64-DFTS-OFDM per sub-band, corresponding to 1024 subcarriers for all 16 sub-bands. The Cyclic Prefix (CP) is just 8 samples (0.83%). Overall spectral efficiency is 8*14/15*0.9917=7.4b/Hz. Taking into account that just 1% of the transmitted data suffices for channel estimation, our final spectral efficiency is 7.34b/Hz. To reduce the PAPR, we use a low-complexity combination of a Partial Transmit Sequence (PTS) algorithm [8] along with optimized clipping (Fig. 2right). Random phases (±1 factors) are applied to each of the 14 data sub-bands. Out of the 214 possible combinations, we verified that 50 random combinations already provide significant improvement of several dB, in exchange for moderate extra complexity and 0.5% SE reduction. The last TX digital stage performs digital high-pass pre-distortion, to compensate for Micram ADC30 and DAC30 roll-off (Fig. 2centerbottom). The novel Rx DSP is detailed in Fig. 3. The basic functions comprise twice-underdecimated analysis Filter Banks (FB) [3] incorporating, at the FB outputs, pilot-assisted [9] CFO and nonlinear phase noise mitigation stages. "Classic" OFDM Rx functions are separately performed (in “Sub-band FPGA processors”), on sub-band basis at 8-fold lower rate. In fact, the two X/Y-FB modules are the only ones operating at full rate. The OFDM receiver functions are: RX timing sync based on Golay sequences [10], DFTS-OFDM de-multiplexing and channel equalization (adaptive LMS based), QAM16 slicer, BER meter, all efficiently implemented in the FPGA HW with innovative solutions for the Golay timing. Although we afforded implementing just a single “Sub-band FPGA processor”, the other 13 processors would be identical, in parallel. The sole sub-band processor is switchable to any FB output, enabling to fully evaluate system performance by accessing and demodulating at will any subband (1.6GHz slice) out of the 25 GHz channel spectrum. Real-Time Implementation All receiver functions (Fig. 3) (except for duplicating identical processor modules for all sub-bands) are real-time implemented resorting to just 3 FPGA chips. FPGA X/Y interfaces to the ADC chips, performs calibration of internal ADC parameters and IQ gain/phase imbalance correction, at system bring-up. Following IQCP 8 Smpls Pr e Di st or t. DFT Spreading Array PTS STAGES OFDM Modulation 64-pnt FFT QAM16 Mapper ±1 64 PN Data 64-pnt FFT QAM16 Mapper ±1 64 PN Data Sub Band1 Sub Band15 1024 Pnt. IFFT SubBand8 Pilot Sub Band16

The need for accurate detection of hostile gun fire location is emphasized in modern low intensity conflicts. Ground forces that work inside densely populated areas cannot rely on soldier alone for the task of identifying friend and foe. An instinctive retaliation of hostile gunfire before the exact source was located may lead to unwanted casualties among the civilians or friendly fire. Muzzle flash detection system will aid in the friend and foe identification task and allow a fast and efficient reaction from the soldier, especially during the daylight, when the muzzle-flash does not contrast with the background and is hardly detectable by human's eye. A new CMOS Single Photon Avalanche Diode (SPAD) imager has been developed at Technion-Israel Institute of Technology and has been reported in the open literature. This paper presents work in progress on prototype of SPAD-based muzzle flash detection system, focusing on the complementary part that controls the imager on-line in real time using FPGA and novel efficient computing architecture.

Interconnect shielding is used in very large scale integration designs to prevent noise interference from the cross-coupling capacitance between adjacent signals. This paper takes advantage of the shields already present in the design and uses them to tune the propagation delay of the clock signals by space tapering, thus eliminating expensive and process variation sensitive dedicated delay buffers. The problem of obtaining the desired delay at a minimum shielding cost (silicon area) by tapering its spacing from the signal wires is solved. A clock-tree synthesis methodology that uses shields to obtain useful skews at the underlying flip-flops is proposed. The method was tested on an industrial 28-nm memory controller and ARM ® processor designs, operated in 800-MHz and 1.6-GHz clock speed, respectively, and confirmed its viability for delivering the required useful skews to flip-flops. About 90% of the useful skew problems could be solved by shielding manipulations.

We present Sound Covert, a novel technique using the machine's audio buffer to secretly (and silently) communicate between applications. Sound Covert can achieve more than 2.6Mbps, four orders of magnitude faster than previously published covert channels. Sound Covert can be used for bidirectional communication between malicious applications anywhere within a given VM (including across users and sand boxes), as well as for sending information from within a VM to an application running on the host OS of the same physical machine. It can also be used for sending information from a compromised external web page to a local malicious application through an innocent, unaltered web browser running in the target application's VM. Similarly, Sound Covert enables a malicious application in a VM that also runs a web server to send data to a malicious partner application running on any machine (or VM) that has a web browser.

In multi-level-cell memory, such as flash and phase-change memory, shrinking cell size and the growing number of levels per cell worsen the access rate to capacity ratio and even reduce access rate. We present minimal maximum-level programming, a scheme for expediting cell programming by sharing physical cells among multiple data sectors and exploiting the fact that making moderate changes to a cell's charge level is faster than making large ones. In particular, we encode the data such that in the k th writing of data to a cell, only the lowest k+1 levels are utilized. Unlike in previously proposed cell-sharing schemes, different same-size data sectors occupy different numbers of physical cells, and a cell may hold a fraction of a bit of a given data sector. Nevertheless, the exposed sector size remains unchanged. Data are encoded, but without redundancy. In a four-level cell example, we achieve up to 75% reduction in write latency. Read latency may be degraded, depending on the percentage of utilized capacity.

Secure computation is increasingly required, most notably when using public clouds. Many secure CPU architectures have been proposed, mostly focusing on single-threaded applications running on a single node. However, security for parallel and distributed computation is also needed, requiring the sharing of secret data among mutually trusting threads running in different compute nodes in an untrusted environment. We propose SDSM, a novel hardware approach for providing secure directory-based distributed shared memory. Unlike previously proposed schemes that cannot maintain reasonable performance beyond 32 cores, our approach allows secure parallel applications to scale efficiently to thousands of cores.

In this paper, we focus on memory in its role as a channel for passing information from one instruction to another; in particular, in conjunction with spatial or dataflow computing architectures, wherein the computing elements are laid out like an assembly plant. We point out the opportunity to dramatically increase effective data access bandwidth by going from a centralized memory array model with a few ports to numerous tiny buffers that can be accessed concurrently. The penalty is loss in access flexibility, but this flexibility is often a by-product of the memory organization rather than a true need. The improvements in hardware reconfiguration speed and resolution, combined with definition of standard buffer queuing and routing capabilities and efforts by tool designers and application developers are likely to extend the applicability of those architectures, offering dramatic power-cost-performance advantages.