To exploit the synergy between the CPU and GPU power management in mobile platforms, several CPU-GPU cooperative DVFS techniques have been proposed recently. Most of those techniques are based on the FPS requirement that may vary depending on the application states dynamically. And they use an analytical model between the processor utilization and the FPS (frames per second) performance of mobile games, which is not easy to obtain. Based on this observation, we propose a novel CPU-GPU cooperative DVFS technique that adaptively detects the FPS requirement at run-time and controls the frequencies accordingly. The proposed adaptation algorithm is composed of three states: learning, tracking, and checking states. In the learning state, the maximum achievable FPS is determined as well as the minimum clock frequencies of the processors. In the tracking state, we adaptively vary the clock frequencies following the minor dynamic fluctuation of the game workload. If the drastic change is detected in the checking state, we go to the learning state again. Experimental results confirm the advantages of the proposed technique over the other techniques.

Building a full system simulator for a CPU-GPU heterogeneous architecture recently draws keen attention of mobile device developers who want to run full software stacks without modification. A common practice is to integrate a GPU simulator with a CPU simulator, which runs very slow or is not applicable when the GPU simulator does not exist. To overcome these drawbacks, a HIL (Hardware-in-the Loop) simulation approach that integrates a real GPU with a CPU simulator has been proposed recently, in which HIL simulation is performed at the device driver level, supporting a specific GPU only. For design space exploration of CPU-GPU heterogeneous architecture, it is necessary to support various GPUs. To this end, we propose a GPU-HIL simulation technique that integrates a real GPU at the OpenGL ES API level, aiming to make a good compromise between speed and timing accuracy. Technical challenges and proposed solutions are presented in detail. Using three OpenGL ES Android benchmarks, preliminary experiments show some use cases of the proposed simulation framework for design space exploration and API-level dynamic behavior monitoring.

Multi-core CPU/GPU heterogeneous platforms became popular in embedded systems. A full system simulator is typically used to observe the internal system behavior by running complete software stacks without modification on simulation models of CPUs and other devices in the system. However, there are few known full system simulators for CPU/GPU heterogeneous platforms and existent GPU simulators are prohibitively slow for running application software. In this paper, we propose a hardware-in-the-loop simulation technique that integrates GPU hardware into a full system simulator. A novel interfacing mechanism between CPU simulator and the development board, where GPU hardware is integrated, is devised. In the experiments, we took Exynos 4412 as a case study, where gem5 simulator is used to simulate mainly a quad-core ARM CPU in the platform and an Exynos development board is used to run the Mali GPU hardware. We could successfully run Android apps on the proposed hardware-in-the-loop simulation framework with up to 1.5 M cycles per second performance.

H.264/AVC video encoders have been widely used for its high coding efficiency. Since the computational demand proportional to the frame resolution is constantly increasing, it has been of great interest to accelerate H.264/AVC by parallel processing. Recently, graphics processing units (GPUs) have emerged as a viable target for accelerating general purpose applications by exploiting fine-grain data parallelisms. Despite extensive research efforts to use GPUs to accelerate the H.264/AVC algorithm, it has not been successful to achieve any speed-up over the x264 algorithm that is known as the fastest CPU implementation, mainly due to significant communication overhead between the host CPU and the GPU and intra-frame dependency in the algorithm. In this paper, we propose a novel motion-estimation (ME) algorithm tailored for NVIDIA GPU implementation. It is accompanied by a novel pipelining technique, called sub-frame ME processing, to effectively hide the communication overhead between the host CPU and the GPU. Further, we incorporate frame-level parallelization technique to improve the overall throughput. Experimental results show that our proposed H.264 encoder has higher performance than x264 encoder.

Emerging mobile devices are likely to adopt CPU-GPU heterogeneous architecture where an embedded GPU executes offloaded computations from the CPU as well as rendering tasks. For design space exploration of such a CPU-GPU heterogeneous architecture at the early design stage or for monitoring the dynamic system behavior of a system, it is very desirable to run the same application software on a full system simulation platform without modification. Since simulations will be performed repetitively, compromise should be made between simulation speed and timing accuracy. Since all known GPU simulators are very slow, in this paper, we propose a hardware-in-the-loop (HIL) simulation framework that integrates the CPU simulator with an existent GPU hardware. A novel interfacing mechanism between the CPU simulator and the GPU hardware is devised to guarantee functional correctness. The proposed technique maintains the timing accuracy of computation workload as much as possible with unavoidable penalty on the timing accuracy of CPU-GPU communication overhead. The proposed simulation framework is implemented with a gem5 full-system simulator and various kinds of GPGPU hardware. For a real-life scenario, we ported the Android platform to the proponativesed simulation framework and ran a face detection application that calls a native function via JNI. The native function can be written in CUDA or OpenCL if it will be offloaded to the GPU, or in Pthreads if it will be run on the CPU. Preliminary experiments show some use cases of the proposed simulation framework for design space exploration and dynamic behavior monitoring.

H.264/AVC video encoders have been widely used for its high coding efficiency. Since the computational demand proportional to the frame resolution is constantly increasing, it has been of great interest to accelerate H.264/AVC by parallel processing. Recently, graphics processing units (GPUs) have emerged as a viable target for accelerating general purpose applications by exploiting fine-grain data parallelisms. Despite extensive research effort to use GPUs to accelerate the H.264/AVC algorithm, it has not been successful to achieve any speed-up over the x264 algorithm that is known as the fastest CPU implementation because of significant communication overhead between the host CPU and the GPU and intra-frame dependency in the algorithm. In this paper, we propose a novel motion estimation (ME) algorithm tailored for NVIDIA GPU implementation. It is accompanied by a novel pipelining technique, called sub-frame ME processing, to effectively hide the communication overhead between the host CPU and the GPU. The proposed H.264 encoder achieves more than 20% speed-up compared with x264.