Chalcogenide-based novel Selector-Only Memory (SOM) has attracted much attention due to its fast-speed performance and manufacturability. However, the lack of endurance, caused by the polarity operation, needs to be improved. Here, we investigate an indium doping scheme for write endurance enhanced and large memory window of GeSe-based SOM. With the evidence of atomic migration, we propose a trade-off relationship between MW and endurance and a relevant model of Se-migration in a restricted range. Based on this model, we demonstrate that less than 5% In-doping can fit the optimization requirements. Besides, the performance of GeSe devices with different In concentrations further confirms the trade-off relationship. Finally, 3% In-doping GeSe SOM devices are fabricated with a large MW (1.3 V), three orders of magnitude improvement of write endurance compared with GeSe devices (10 6 ) and excellent read endurance (10 9 ). This work helps the endurance optimization of SOM devices and is promising to accelerate its widespread application.

Artificial neural networks (ANNs) have recently made a significant impact on the field of industrial electronics. Increasing efforts have been focused on implementing ANN using more efficient and compact architectures to achieve improved computational performance and power efficiency. The activation function of the nonlinear layers is crucial for the successful implementation of ANN, as it enables the network to possess generalization ability. In this study, we implemented the hyperbolic tangent function (tanh) using an analog circuit based on phase-change memory (PCM), which is a mature nonvolatile technology. This fully analog PCM-based tanh function is naturally compatible with analog-memory-based ANN architectures, such as the memristive neural networks (MNNs). An analog circuit has been proposed to implement the tanh by transforming the PCM I-V characteristics. The results indicate that the implemented tanh based on PCM presents a low root-mean-square error to the ideal tanh. Furthermore, the performance of the implemented tanh was verified in a classical deep neural network (DNN) with the handwritten digit recognition task. The implemented tanh with realistic characteristics presents a training accuracy (>90%) and good precision for repeatability inference in DNN. This work provides effective means for implementing activation functions in ANN based on analog memory.

Multifunctional neuromorphic devices to tackle complex tasks are highly desirable for the development of artificial neural networks. Threshold switching (TS) memory, which exhibits volatile abrupt resistance change under external electric fields, is capable of emulating multiple biological behaviors because of its rich temporal dynamics. Here, a TS device based on two-dimensional (2D) SnSe is demonstrated. Owing to the diffusive dynamics of Ag ions in SnSe, intrinsic stochasticity of the TS behavior is observed, which can be exploited to construct a compact stochastic Leaky-Integrate and Fire (LIF) model with improved performance in spiking neuron network (SNN). Moreover, an artificial nociceptor is constructed based on the 2D TS device, successfully emulating typical nociceptive features of "threshold", "relaxation", "no adaptation", "hyperalgesia" and "allodynia". The realization of bioinspired devices with combined sensory and information processing abilities paves the way for developing neuromorphic electronics for SNN and humanoid robots.

The artificial nociceptor is a device that simulates the biological nociception system, which has a wide range of applications in the fields of medicine, rehabilitation, and robotics. Multimodal nociceptors can respond to diverse stimuli, including visual, mechanical, and thermal, and so on, and then convert them into neural signals for processing by the brain. Herein, a back-gate optoelectronic transistor based on 2D InSe/MoS2 heterostructure is demonstrated. By employing energy band alignment of the heterojunction, the device exhibits high sensitivity (10(6)) and high responsivity (330 AW(-1)) to harmful UV irradiation, which can be exploited to emulate the key features of nociceptors, including "threshold," "relaxation," "no adaptation," and "sensitization." Moreover, the device can be operated in a two-terminal mode, memristive characteristics are obtained through applying source-drain voltages. Then, artificial nociceptive behaviors responding to external electrical pulses have been successfully emulated. Finally, the modulation of nociceptive sensitivity can be achieved through the controlling gate bias, which fully demonstrates the potential of our device for the application of biomimetic multimodal artificial nociceptors in future neuromorphic sensory system.

Ovonic threshold switch (OTS) selector is a key enabler for developing high-density nonvolatile memory with crossbar arrays. In this work, we investigated the resistance characteristics of the OTS device at the ON state, which is pivotal in the integration of the OTS and the memory element. The results indicate that the ON-resistance is not a constant value in the OTS device and is uncorrelated with the device areas but dependent on the real-time power applied on the device that is at ON state. Then, we proposed a thermal-induced compact model to describe the ON-resistance in the OTS device, referring to the simulation of the expansive conductive channel in OTS. The proposed model matches well with the measured ON-resistances with different conditions in the study. Our results contribute to further understanding of the threshold switching mechanism and selecting appropriate operation conditions for the OTS selector integrated in the high-density memory array.

Further improvement of storage density is a key challenge for the application of phase-change memory (PCM) in storage-class memory. However, for PCM, storage density improvements include feature size scaling down and multi-level cell (MLC) operation, potentially causing thermal crosstalk issues and phase separation issues, respectively. To address these challenges, we propose a high-aspect-ratio (25:1) lateral nanowire (NW) PCM device with conventional chalcogenide Ge2Sb2Te5 (GST-225) to realize stable MLC operations, i.e., low intra- and inter-cell variability and low resistance drift (coefficient = 0.009). The improved MLC performance is attributed to the high aspect ratio, which enables precise control of the amorphous region because of sidewall confinement, as confirmed by transmission electron microscopy analysis. In summary, the NW devices provide guidance for the design of future high-aspect-ratio three-dimensional PCM devices with MLC capability.

In this work, we studied the threshold voltage ${V} _{\text {th}}$ for an ovonic threshold switch (OTS) device in a high-frequency continuous operation. By applying a pulse sequence with small pulse intervals, the dependence of ${V} _{\text {th}}$ on the falling edge of the prior pulse has been investigated in the Te-based OTS device. The results indicate that the ${V} _{\text {th}}$ presents a Weibull distribution in the pulse sequence, and the ${V} _{\text {th}}$ distribution drifts nonmonotonically with the pulse falling edge. Meanwhile, the drift tendency of the ${V} _{\text {th}}$ distribution was found depending on the device area. Furthermore, the recovery process and the time-resolved current profiles in the device operation have been investigated to further study the ${V} _{\text {th}}$ drift. The results indicate that the ${V} _{\text {th}}$ drift in continuous device operation is controllable and results from a combination of the effects of heat accumulation and the recovery process. The ${V} _{\text {th}}$ drift at high-frequency operating can be reduced by optimizing the device lateral dimension according to the mapping results of the ${V} _{\text {th}}$ . Our results can guide the design and operation of the OTS device with a low ${V} _{\text {th}}$ drift requirement.

In this work, the time-delay effect on device operation caused by capacitance is studied in terms of phase-change memory (PCM) integrated with an ovonic threshold switch (OTS) selector. The capacitance studied in this work is the intrinsic capacitance associated with capacitive reactance of the PCM itself. The capacitance of the PCM in the amorphous state was measured, and it presents an exponential dependence on voltage bias. Through the simulation model of an OTS-PCM integrated device that considering the measured capacitance behavior, the time-delay characteristics of the integrated device for the SET process with various pulses were investigated. Results indicate that the onset of the threshold switching (TS) is delayed in the PCM but occurs early in the OTS with capacitance in the integrated device. In addition, it is found that the variable capacitance behavior can not only minimize the delay effect, but also accelerate the SET operation under certain conditions in the integrated device. Our results can provide practical guidance for the design of fast operating devices.

In this paper, we present a multiple layer device for investigating the impact of electric field on the conductance switching of GeTe phase change material excluding the contribution from Joule heat. The device includes a dielectric layer with excellent current-blocking which can result in a large electric field generated in the amorphous GeTe film and almost no current. With the generated electric field far beyond its threshold value for the conductance switching, our experimental data indicate that the conductance switching has not happened in the GeTe film. This indicates that the ovonic threshold switching (OTS) could not be induced by the purely electric field in amorphous chalcogenide film. Meanwhile, a modified thermal-assist model based on the Poole–Frenkel (PF) mechanism has been proposed to verify the thermal assistance is indispensable in the OTS process. And the modified model is well applied on the GeTe devices with different scales, which further supports the current experimental conclusion. This contributes to the further study of the OTS mechanism and application of the phase-change memory (PCM).

We present a finite-element model for the confined-structure device integrating a phase change memory (PCM) and an ovonic threshold switch (OTS) selector. In this model, the threshold switching (TS) characteristics of the PCM and OTS were described by an embedded numerical model to simulate the operation of the integrated device. Both the SET and RESET processes have been well implemented in the integrated device by simulating. The electronic properties of the integrated device with various OTS material parameters have been investigated by simulating. Based on the simulated results, a moderate set-pulse has been obtained by optimizing only the OTS conductivity at a high-conductivity state. Further simulations for multilevel storage have been carried out in the integrated device based on the optimized OTS. The results indicate the confined-structure device with a larger length-diameter ratio will result in a more flexible operation window for multilevel storage. Particularly, when the length-diameter ratio of the confined-structure is 2:1 in the integrated device, five levels of device resistance could be obtained in the simulations of multilevel storage by applying multiple set-pulse or reset-pulse. This could guide further studies on the multilevel storage.