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Robert S. Orefice (M'00) received the B.S. degree in computer engineering from Rochester Institute of Technology, Rochester, NY, in 2002 and the M.S. degree from the NTU School of Engineering at Walden University in 2005.
In 1999, he joined AMD in Austin, TX, where he worked on BIOS software development, Northbridge chipset design, and digital logic for the floating point unit on the K8 CPU. He relocated to Boxborough, MA, in 2004 where he continued design work for the K8 and Bulldozer Cores and contributed to methodology. In 2008, he joined Achronix Semiconductor in Cambridge, MA, where he worked on design and CAD tool development for asynchronous circuits. He rejoined AMD in 2010 where he implemented distributed power gating logic on the Steamroller core and worked on physical design construction methodology. He has one other IEEE publication.
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2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC) (2014): 104-+
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#Papers: 4
#Citation: 89
H-Index: 3
G-Index: 3
Sociability: 3
Diversity: 1
Activity: 0
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