3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

IBM Journal of Research and Development, pp. 611-622, 2008.

Cited by: 107|Views27
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Abstract:

Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip...More

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